index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
arch
/
riscv
/
kernel
Age
Commit message (
Expand
)
Author
Files
Lines
2018-10-23
RISC-V: SMP cleanup and new features
Palmer Dabbelt
7
-47
/
+195
2018-10-23
RISC-V: Fix some RV32 bugs and build failures
Palmer Dabbelt
1
-0
/
+3
2018-10-23
riscv: Add support to no-FPU systems
Palmer Dabbelt
6
-115
/
+168
2018-10-23
RISC-V: remove the unused return_to_handler export
Christoph Hellwig
1
-1
/
+0
2018-10-23
RISC-V: Add FP register ptrace support for gdb.
Jim Wilson
1
-0
/
+52
2018-10-23
RISC-V: Mask out the F extension on systems without D
Palmer Dabbelt
1
-0
/
+7
2018-10-23
RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}
Palmer Dabbelt
1
-7
/
+0
2018-10-23
RISC-V: Show IPI stats
Anup Patel
2
-7
/
+40
2018-10-23
RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo
Anup Patel
1
-4
/
+6
2018-10-23
RISC-V: Use Linux logical CPU number instead of hartid
Atish Patra
5
-22
/
+45
2018-10-23
RISC-V: Add logical CPU indexing for RISC-V
Atish Patra
2
-0
/
+23
2018-10-23
RISC-V: Use WRITE_ONCE instead of direct access
Atish Patra
1
-2
/
+3
2018-10-23
RISC-V: Use mmgrab()
Palmer Dabbelt
1
-1
/
+2
2018-10-23
RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu
Palmer Dabbelt
1
-4
/
+5
2018-10-23
RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid
Palmer Dabbelt
2
-3
/
+6
2018-10-23
RISC-V: Disable preemption before enabling interrupts
Atish Patra
1
-1
/
+5
2018-10-23
RISC-V: Comment on the TLB flush in smp_callin()
Palmer Dabbelt
1
-0
/
+4
2018-10-23
RISC-V: Filter ISA and MMU values in cpuinfo
Palmer Dabbelt
1
-7
/
+61
2018-10-23
RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}
Palmer Dabbelt
1
-7
/
+0
2018-10-23
RISC-V: No need to pass scause as arg to do_IRQ()
Anup Patel
2
-3
/
+2
2018-10-23
RISC-V: Use swiotlb on RV64 only
Zong Li
1
-0
/
+3
2018-10-23
Auto-detect whether a FPU exists
Alan Kao
3
-3
/
+15
2018-10-23
Allow to disable FPU support
Alan Kao
3
-2
/
+9
2018-10-23
Refactor FPU code in signal setup/return procedures
Alan Kao
1
-27
/
+41
2018-10-23
Extract FPU context operations from entry.S
Alan Kao
3
-87
/
+107
2018-10-02
RISCV: Fix end PFN for low memory
Atish Patra
1
-1
/
+1
2018-09-05
riscv: Do not overwrite initrd_start and initrd_end
Guenter Roeck
1
-7
/
+0
2018-08-28
RISC-V: Use a less ugly workaround for unused variable warnings
Palmer Dabbelt
1
-14
/
+1
2018-08-20
RISC-V: Define sys_riscv_flush_icache when SMP=n
Palmer Dabbelt
1
-2
/
+10
2018-08-13
RISC-V: Fix !CONFIG_SMP compilation error
Atish Patra
1
-1
/
+0
2018-08-13
RISC-V: Add the directive for alignment of stvec's value
Zong Li
1
-0
/
+2
2018-08-13
clocksource: new RISC-V SBI timer driver
Palmer Dabbelt
3
-9
/
+4
2018-08-13
RISC-V: implement low-level interrupt handling
Christoph Hellwig
2
-11
/
+45
2018-08-13
RISC-V: simplify software interrupt / IPI code
Christoph Hellwig
1
-4
/
+2
2018-08-13
RISC-V: remove timer leftovers
Christoph Hellwig
1
-21
/
+0
2018-08-13
RISC-V: Add early printk support via the SBI console
Palmer Dabbelt
1
-0
/
+27
2018-08-13
RISC-V: Don't increment sepc after breakpoint.
Jim Wilson
1
-1
/
+0
2018-08-13
RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building the vDSO
Palmer Dabbelt
1
-2
/
+2
2018-07-05
RISC-V: Fix the rv32i kernel build
Palmer Dabbelt
1
-11
/
+11
2018-07-05
RISC-V: Fix PTRACE_SETREGSET bug.
Jim Wilson
1
-1
/
+1
2018-07-05
RISC-V: Don't include irq-riscv-intc.h
Palmer Dabbelt
1
-4
/
+0
2018-07-05
riscv: remove unnecessary of_platform_populate call
Rob Herring
1
-5
/
+0
2018-07-05
RISC-V: fix R_RISCV_ADD32/R_RISCV_SUB32 relocations
Andreas Schwab
1
-2
/
+2
2018-07-04
RISC-V: Change variable type for 32-bit compatible
Zong Li
1
-11
/
+11
2018-06-16
Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm...
Linus Torvalds
6
-3
/
+503
2018-06-11
RISC-V: Make our port sparse-clean
Palmer Dabbelt
2
-2
/
+3
2018-06-11
RISC-V: Handle R_RISCV_32 in modules
Andreas Schwab
1
-0
/
+12
2018-06-11
riscv/ftrace: Export _mcount when DYNAMIC_FTRACE isn't set
Alan Kao
1
-1
/
+1
2018-06-09
riscv: split the declaration of __copy_user
Luc Van Oostenryck
1
-1
/
+2
2018-06-08
Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...
Linus Torvalds
1
-1
/
+0
[next]