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:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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/
arch
/
riscv
/
kernel
/
traps.c
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Commit message (
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Author
Files
Lines
2019-07-09
Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds
1
-5
/
+6
2019-06-05
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
Thomas Gleixner
1
-9
/
+1
2019-05-29
signal: Remove the task parameter from force_sig_fault
Eric W. Biederman
1
-2
/
+2
2019-05-29
signal: Explicitly call force_sig_fault on current
Eric W. Biederman
1
-1
/
+1
2019-05-29
signal/riscv: Remove tsk parameter from do_trap
Eric W. Biederman
1
-3
/
+4
2019-05-17
riscv: Support BUG() in kernel module
Vincent Chen
1
-1
/
+1
2019-05-17
riscv: Add the support for c.ebreak check in is_valid_bugaddr()
Vincent Chen
1
-3
/
+17
2019-05-17
RISC-V: Access CSRs using CSR numbers
Anup Patel
1
-3
/
+3
2019-04-26
riscv: remove duplicate macros from ptrace.h
Christoph Hellwig
1
-1
/
+1
2018-08-13
RISC-V: Don't increment sepc after breakpoint.
Jim Wilson
1
-1
/
+0
2018-06-16
Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm...
Linus Torvalds
1
-1
/
+1
2018-06-07
riscv: no __user for probe_kernel_address()
Luc Van Oostenryck
1
-1
/
+1
2018-04-25
signal/riscv: Replace do_trap_siginfo with force_sig_fault
Eric W. Biederman
1
-8
/
+2
2018-04-25
signal/riscv: Use force_sig_fault where appropriate
Eric W. Biederman
1
-8
/
+1
2018-04-25
signal: Ensure every siginfo we send has all bits initialized
Eric W. Biederman
1
-0
/
+1
2017-09-27
RISC-V: Init and Halt Code
Palmer Dabbelt
1
-0
/
+180