index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
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path:
root
/
arch
/
riscv
/
kernel
/
smpboot.c
Age
Commit message (
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)
Author
Files
Lines
2019-03-04
RISC-V: Compare cpuid with NR_CPUS before mapping.
Atish Patra
1
-0
/
+5
2019-03-04
RISC-V: Do not wait indefinitely in __cpu_up
Atish Patra
1
-3
/
+12
2019-02-12
riscv: use for_each_of_cpu_node iterator
Johan Hovold
1
-2
/
+2
2019-01-23
RISC-V: fix bad use of of_node_put
Andreas Schwab
1
-5
/
+1
2018-12-21
RISC-V: Fix of_node_* refcount
Atish Patra
1
-1
/
+5
2018-10-23
RISC-V: Use Linux logical CPU number instead of hartid
Atish Patra
1
-9
/
+16
2018-10-23
RISC-V: Use WRITE_ONCE instead of direct access
Atish Patra
1
-2
/
+3
2018-10-23
RISC-V: Use mmgrab()
Palmer Dabbelt
1
-1
/
+2
2018-10-23
RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu
Palmer Dabbelt
1
-4
/
+5
2018-10-23
RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid
Palmer Dabbelt
1
-1
/
+1
2018-10-23
RISC-V: Disable preemption before enabling interrupts
Atish Patra
1
-1
/
+5
2018-10-23
RISC-V: Comment on the TLB flush in smp_callin()
Palmer Dabbelt
1
-0
/
+4
2018-08-13
clocksource: new RISC-V SBI timer driver
Palmer Dabbelt
1
-1
/
+0
2017-09-27
RISC-V: Init and Halt Code
Palmer Dabbelt
1
-0
/
+114