starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2018-10-23	RISC-V: SMP cleanup and new features	Palmer Dabbelt	1	-0/+10
2018-10-23	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra	1	-0/+6
2018-10-23	RISC-V: Add logical CPU indexing for RISC-V	Atish Patra	1	-0/+4
2018-10-23	RISC-V: Use swiotlb on RV64 only	Zong Li	1	-0/+3
2018-10-02	RISCV: Fix end PFN for low memory	Atish Patra	1	-1/+1
2018-09-05	riscv: Do not overwrite initrd_start and initrd_end	Guenter Roeck	1	-7/+0
2018-08-13	RISC-V: Add early printk support via the SBI console	Palmer Dabbelt	1	-0/+27
2018-07-05	riscv: remove unnecessary of_platform_populate call	Rob Herring	1	-5/+0
2018-05-19	riscv: add swiotlb support	Christoph Hellwig	1	-0/+2
2018-02-20	Rename sbi_save to parse_dtb to improve code readability	Michael Clark	1	-1/+1
2018-01-31	riscv: add ZONE_DMA32	Christoph Hellwig	1	-0/+9
2018-01-31	RISC-V: Remove mem_end command line processing	Palmer Dabbelt	1	-19/+0
2018-01-31	RISC-V: Remove duplicate command-line parsing logic	Michael Clark	1	-16/+0
2017-12-11	RISC-V: Remove unused CONFIG_HVC_RISCV_SBI code	Palmer Dabbelt	1	-11/+0
2017-11-30	RISC-V: Export some expected symbols for modules	Olof Johansson	1	-0/+2
2017-11-30	RISC-V: move empty_zero_page definition to C and export it	Olof Johansson	1	-0/+3
2017-09-27	RISC-V: Init and Halt Code	Palmer Dabbelt	1	-0/+257