| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2020-01-05 | riscv: prefix IRQ_ macro names with an RV_ namespace | Paul Walmsley | 1 | -3/+3 |
| 2019-11-05 | riscv: abstract out CSR names for supervisor vs machine mode | Christoph Hellwig | 1 | -12/+5 |
| 2019-10-28 | riscv: for C functions called only from assembly, mark with __visible | Paul Walmsley | 1 | -1/+1 |
| 2019-05-17 | RISC-V: Add interrupt related SCAUSE defines in asm/csr.h | Anup Patel | 1 | -12/+4 |
| 2019-04-26 | riscv: print the unexpected interrupt cause | Christoph Hellwig | 1 | -1/+2 |
| 2018-10-23 | RISC-V: Show IPI stats | Anup Patel | 1 | -0/+8 |
| 2018-10-23 | RISC-V: No need to pass scause as arg to do_IRQ() | Anup Patel | 1 | -2/+2 |
| 2018-08-13 | clocksource: new RISC-V SBI timer driver | Palmer Dabbelt | 1 | -0/+3 |
| 2018-08-13 | RISC-V: implement low-level interrupt handling | Christoph Hellwig | 1 | -9/+43 |
| 2018-07-05 | RISC-V: Don't include irq-riscv-intc.h | Palmer Dabbelt | 1 | -4/+0 |
| 2018-03-14 | RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler | Palmer Dabbelt | 1 | -13/+0 |
| 2017-09-27 | RISC-V: Init and Halt Code | Palmer Dabbelt | 1 | -0/+39 |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
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