starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	1	-9/+1
2019-05-17	RISC-V: Access CSRs using CSR numbers	Anup Patel	1	-11/+11
2019-01-23	RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=y	Vincent Chen	1	-1/+17
2019-01-07	riscv: add audit support	David Abdurachmanov	1	-2/+2
2018-10-23	RISC-V: SMP cleanup and new features	Palmer Dabbelt	1	-1/+0
2018-10-23	RISC-V: No need to pass scause as arg to do_IRQ()	Anup Patel	1	-1/+0
2018-10-23	Extract FPU context operations from entry.S	Alan Kao	1	-87/+0
2018-08-13	RISC-V: implement low-level interrupt handling	Christoph Hellwig	1	-2/+2
2018-03-14	RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler	Palmer Dabbelt	1	-4/+3
2018-02-20	RISC-V: Enable IRQ during exception handling	zongbox@gmail.com	1	-2/+3
2018-01-31	riscv: disable SUM in the exception handler	Christoph Hellwig	1	-3/+6
2018-01-08	riscv: rename SR_* constants to match the spec	Christoph Hellwig	1	-4/+4
2017-09-27	RISC-V: Task implementation	Palmer Dabbelt	1	-0/+464