| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-01-07 | riscv: add audit support | David Abdurachmanov | 1 | -2/+2 |
| 2018-10-23 | RISC-V: SMP cleanup and new features | Palmer Dabbelt | 1 | -1/+0 |
| 2018-10-23 | RISC-V: No need to pass scause as arg to do_IRQ() | Anup Patel | 1 | -1/+0 |
| 2018-10-23 | Extract FPU context operations from entry.S | Alan Kao | 1 | -87/+0 |
| 2018-08-13 | RISC-V: implement low-level interrupt handling | Christoph Hellwig | 1 | -2/+2 |
| 2018-03-14 | RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler | Palmer Dabbelt | 1 | -4/+3 |
| 2018-02-20 | RISC-V: Enable IRQ during exception handling | zongbox@gmail.com | 1 | -2/+3 |
| 2018-01-31 | riscv: disable SUM in the exception handler | Christoph Hellwig | 1 | -3/+6 |
| 2018-01-08 | riscv: rename SR_* constants to match the spec | Christoph Hellwig | 1 | -4/+4 |
| 2017-09-27 | RISC-V: Task implementation | Palmer Dabbelt | 1 | -0/+464 |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |