starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2020-04-09	Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/...	Linus Torvalds	1	-82/+61
2020-03-06	riscv: fix seccomp reject syscall code path	Tycho Andersen	1	-8/+3
2020-03-03	RISC-V: Inline the assembly register save/restore macros	Palmer Dabbelt	1	-82/+61
2020-01-28	Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	1	-2/+2
2019-12-28	riscv: reject invalid syscalls below -1	David Abdurachmanov	1	-0/+1
2019-12-08	sched/rt, riscv: Use CONFIG_PREEMPTION	Thomas Gleixner	1	-2/+2
2019-11-23	Merge branch 'next/nommu' into for-next	Paul Walmsley	1	-31/+54
2019-11-18	riscv: add nommu support	Christoph Hellwig	1	-0/+11
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig	1	-31/+43
2019-10-29	riscv: add support for SECCOMP and SECCOMP_FILTER	David Abdurachmanov	1	-2/+25
2019-10-10	RISC-V: entry: Remove unneeded need_resched() loop	Valentin Schneider	1	-2/+1
2019-10-01	RISC-V: Clear load reservations while restoring hart contexts	Palmer Dabbelt	1	-1/+20
2019-09-20	riscv: Avoid interrupts being erroneously enabled in handle_exception()	Vincent Chen	1	-1/+5
2019-08-30	riscv: Using CSR numbers to access CSRs	Bin Meng	1	-3/+3
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	1	-9/+1
2019-05-17	RISC-V: Access CSRs using CSR numbers	Anup Patel	1	-11/+11
2019-01-23	RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=y	Vincent Chen	1	-1/+17
2019-01-07	riscv: add audit support	David Abdurachmanov	1	-2/+2
2018-10-23	RISC-V: SMP cleanup and new features	Palmer Dabbelt	1	-1/+0
2018-10-23	RISC-V: No need to pass scause as arg to do_IRQ()	Anup Patel	1	-1/+0
2018-10-23	Extract FPU context operations from entry.S	Alan Kao	1	-87/+0
2018-08-13	RISC-V: implement low-level interrupt handling	Christoph Hellwig	1	-2/+2
2018-03-14	RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler	Palmer Dabbelt	1	-4/+3
2018-02-20	RISC-V: Enable IRQ during exception handling	zongbox@gmail.com	1	-2/+3
2018-01-31	riscv: disable SUM in the exception handler	Christoph Hellwig	1	-3/+6
2018-01-08	riscv: rename SR_* constants to match the spec	Christoph Hellwig	1	-4/+4
2017-09-27	RISC-V: Task implementation	Palmer Dabbelt	1	-0/+464