starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2020-05-05	RISC-V: Add bitmap reprensenting ISA features common across CPUs	Anup Patel	1	-3/+80
2019-10-28	riscv: add missing header file includes	Paul Walmsley	1	-0/+1
2019-06-19	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234	Thomas Gleixner	1	-12/+1
2019-03-04	RISC-V: Assign hwcap as per comman capabilities.	Atish Patra	1	-19/+22
2019-02-12	riscv: use for_each_of_cpu_node iterator	Johan Hovold	1	-2/+3
2019-02-12	riscv: add missing newlines to printk messages	Johan Hovold	1	-4/+4
2018-12-21	RISC-V: Fix of_node_* refcount	Atish Patra	1	-0/+2
2018-10-31	RISC-V: properly determine hardware caps	Andreas Schwab	1	-3/+5
2018-10-23	riscv: Add support to no-FPU systems	Palmer Dabbelt	1	-0/+8
2018-10-23	RISC-V: Mask out the F extension on systems without D	Palmer Dabbelt	1	-0/+7
2018-10-23	Auto-detect whether a FPU exists	Alan Kao	1	-0/+8
2017-09-27	RISC-V: User-facing API	Palmer Dabbelt	1	-0/+61