starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2022-05-12	riscv: add RISC-V Svpbmt extension support	Heiko Stuebner	1	-0/+1
2022-04-01	riscv: cpu.c: don't use kernel-doc markers for comments	Randy Dunlap	1	-2/+2
2022-03-31	RISC-V: Fix a comment typo in riscv_of_parent_hartid()	Atish Patra	1	-1/+1
2022-03-22	perf: RISC-V: Add support for SBI PMU and Sscofpmf	Palmer Dabbelt	1	-0/+1
2022-03-22	RISC-V: Add sscofpmf extension support	Atish Patra	1	-0/+1
2022-03-18	RISC-V: Provide a fraemework for RISC-V ISA extensions	Palmer Dabbelt	1	-2/+63
2022-03-17	RISC-V: Improve /proc/cpuinfo output for ISA extensions	Atish Patra	1	-2/+63
2022-02-15	riscv: mm: Set sv57 on defaultly	Qinglin Pan	1	-1/+3
2022-01-20	riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfo	Alexandre Ghiti	1	-11/+12
2021-10-20	riscv: Use of_get_cpu_hwid()	Rob Herring	1	-1/+2
2020-06-10	RISC-V: Rename and move plic_find_hart_id() to arch directory	Anup Patel	1	-0/+16
2019-10-28	RISC-V: Remove unsupported isa string info print	Atish Patra	1	-42/+3
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	1	-9/+1
2019-04-30	RISC-V: Add RISC-V specific arch_match_cpu_phys_id	Atish Patra	1	-2/+1
2019-03-04	RISC-V: Remove NR_CPUs check during hartid search from DT	Atish Patra	1	-4/+0
2019-02-12	riscv: treat cpu devicetree nodes without status as enabled	Johan Hovold	1	-7/+3
2019-02-12	riscv: fix riscv_of_processor_hartid() comment	Johan Hovold	1	-9/+9
2019-02-12	riscv: add missing newlines to printk messages	Johan Hovold	1	-1/+1
2018-12-21	RISC-V: Fix of_node_* refcount	Atish Patra	1	-0/+1
2018-11-20	RISC-V: recognize S/U mode bits in print_isa	Patrick Stählin	1	-3/+6
2018-10-23	RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo	Anup Patel	1	-4/+6
2018-10-23	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra	1	-3/+5
2018-10-23	RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid	Palmer Dabbelt	1	-2/+5
2018-10-23	RISC-V: Filter ISA and MMU values in cpuinfo	Palmer Dabbelt	1	-7/+61
2017-09-27	RISC-V: Init and Halt Code	Palmer Dabbelt	1	-0/+108