| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2018-11-20 | RISC-V: recognize S/U mode bits in print_isa | Patrick Stählin | 1 | -3/+6 |
| 2018-10-23 | RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo | Anup Patel | 1 | -4/+6 |
| 2018-10-23 | RISC-V: Use Linux logical CPU number instead of hartid | Atish Patra | 1 | -3/+5 |
| 2018-10-23 | RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid | Palmer Dabbelt | 1 | -2/+5 |
| 2018-10-23 | RISC-V: Filter ISA and MMU values in cpuinfo | Palmer Dabbelt | 1 | -7/+61 |
| 2017-09-27 | RISC-V: Init and Halt Code | Palmer Dabbelt | 1 | -0/+108 |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |