starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2019-09-17	Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...	Linus Torvalds	7	-60/+96
2019-09-14	riscv: modify the Image header to improve compatibility with the ARM64 header	Paul Walmsley	1	-6/+6
2019-09-05	riscv: move the TLB flush logic out of line	Christoph Hellwig	1	-30/+7
2019-09-05	riscv: don't use the rdtime(h) pseudo-instructions	Christoph Hellwig	1	-23/+21
2019-09-05	riscv: cleanup riscv_cpuid_to_hartid_mask	Christoph Hellwig	2	-7/+0
2019-09-05	riscv: Add support for perf registers sampling	Mao Han	1	-0/+42
2019-08-30	RISC-V: Implement sparsemem	Logan Gunthorpe	3	-0/+26
2019-08-29	RISC-V: Fix FIXMAP area corruption on RV32 systems	Anup Patel	2	-6/+10
2019-08-14	riscv: Make __fstate_clean() work correctly.	Vincent Chen	1	-1/+1
2019-08-14	riscv: Correct the initialized flow of FP register	Vincent Chen	1	-0/+6
2019-08-14	riscv: fix flush_tlb_range() end address for flush_tlb_page()	Paul Walmsley	1	-2/+9
2019-07-28	Merge tag 'spdx-5.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/gre...	Linus Torvalds	7	-7/+7
2019-07-25	treewide: add "WITH Linux-syscall-note" to SPDX tag of uapi headers	Masahiro Yamada	7	-7/+7
2019-07-22	riscv: include generic support for MSI irqdomains	Wesley Terpstra	1	-0/+1
2019-07-19	riscv: enable sys_clone3 syscall for rv64	Paul Walmsley	1	-0/+1
2019-07-18	Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...	Linus Torvalds	7	-10/+176
2019-07-18	riscv: fix build break after macro-to-function conversion in generic cacheflu...	Paul Walmsley	1	-4/+59
2019-07-12	riscv: switch to generic version of pte allocation	Mike Rapoport	1	-27/+2
2019-07-11	RISC-V: Add an Image header that boot loader can parse.	Atish Patra	1	-0/+65
2019-07-11	Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg...	Linus Torvalds	1	-0/+1
2019-07-09	RISC-V: Setup initial page tables in two stages	Anup Patel	3	-0/+18
2019-07-09	Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...	Linus Torvalds	1	-1/+1
2019-07-09	Merge branch 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/k...	Linus Torvalds	1	-21/+23
2019-07-04	riscv: Introduce huge page support for 32/64bit kernel	Alexandre Ghiti	3	-2/+34
2019-07-01	riscv: Remove gate area stubs	Andy Lutomirski	1	-4/+0
2019-06-24	riscv: add binfmt_flat support	Christoph Hellwig	1	-0/+1
2019-06-21	Merge tag 'spdx-5.2-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gre...	Linus Torvalds	8	-96/+8
2019-06-19	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234	Thomas Gleixner	8	-96/+8
2019-06-17	Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/ke...	Linus Torvalds	1	-5/+0
2019-06-17	riscv: remove unused barrier defines	Rolf Eike Beer	1	-5/+0
2019-06-17	Merge tag 'v5.2-rc5' into locking/core, to pick up fixes	Ingo Molnar	40	-359/+40
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	40	-359/+40
2019-06-03	locking/atomic, riscv: Use s64 for atomic64	Mark Rutland	1	-21/+23
2019-06-03	locking/atomic, riscv: Fix atomic64_sub_if_positive() offset argument	Mark Rutland	1	-1/+1
2019-05-30	treewide: Add SPDX license identifier - Kbuild	Greg Kroah-Hartman	2	-0/+2
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	Thomas Gleixner	1	-9/+1
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152	Thomas Gleixner	1	-5/+1
2019-05-29	signal/riscv: Remove tsk parameter from do_trap	Eric W. Biederman	1	-1/+1
2019-05-24	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 36	Thomas Gleixner	1	-5/+1
2019-05-19	Merge tag 'kbuild-v5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ma...	Linus Torvalds	1	-4/+0
2019-05-19	Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	13	-181/+156
2019-05-18	arch: remove dangling asm-generic wrappers	Masahiro Yamada	1	-4/+0
2019-05-17	RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs	Yash Shah	1	-0/+16
2019-05-17	riscv: Add the support for c.ebreak check in is_valid_bugaddr()	Vincent Chen	1	-1/+6
2019-05-17	riscv: support trap-based WARN()	Vincent Chen	1	-10/+18
2019-05-17	riscv: fix sbi_remote_sfence_vma{,_asid}.	Gary Guo	1	-7/+12
2019-05-17	riscv: move switch_mm to its own file	Gary Guo	1	-52/+2
2019-05-17	riscv: move flush_icache_{all,mm} to cacheflush.c	Gary Guo	1	-1/+1
2019-05-17	RISC-V: Access CSRs using CSR numbers	Anup Patel	3	-18/+31
2019-05-17	RISC-V: Add interrupt related SCAUSE defines in asm/csr.h	Anup Patel	1	-4/+17