starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2022-01-20	RISC-V: Do not use cpumask data structure for hartid bitmap	Atish Patra	1	-2/+0
2022-01-09	RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=n	Sean Christopherson	1	-8/+2
2022-01-09	riscv: remove cpu_stop()	Jisheng Zhang	1	-2/+0
2021-04-26	riscv: Constify sbi_ipi_ops	Jisheng Zhang	1	-2/+2
2020-08-20	RISC-V: Add mechanism to provide custom IPI operations	Anup Patel	1	-0/+19
2020-08-05	RISC-V: Fix build warning for smpboot.c	Atish Patra	1	-0/+3
2020-06-10	RISC-V: self-contained IPI handling routine	Anup Patel	1	-0/+3
2020-03-31	RISC-V: Support cpu hotplug	Atish Patra	1	-0/+17
2020-03-31	RISC-V: Implement new SBI v0.2 extensions	Atish Patra	1	-0/+7
2019-09-05	riscv: cleanup riscv_cpuid_to_hartid_mask	Christoph Hellwig	1	-6/+0
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	1	-9/+1
2019-03-04	RISC-V: Move cpuid to hartid mapping to SMP.	Atish Patra	1	-5/+13
2018-10-23	RISC-V: Show IPI stats	Anup Patel	1	-0/+9
2018-10-23	RISC-V: Add logical CPU indexing for RISC-V	Atish Patra	1	-1/+23
2018-10-23	RISC-V: Provide a cleaner raw_smp_processor_id()	Palmer Dabbelt	1	-10/+4
2018-08-13	clocksource: new RISC-V SBI timer driver	Palmer Dabbelt	1	-3/+0
2018-08-13	RISC-V: simplify software interrupt / IPI code	Christoph Hellwig	1	-3/+0
2017-09-27	RISC-V: Init and Halt Code	Palmer Dabbelt	1	-0/+52