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2022-09-27riscv: dts: microchip: icicle: re-jig fabric peripheral addressesConor Dooley1-4/+4
When users try to add onto the reference design, they find that the current addresses that peripherals connected to Fabric InterConnect (FIC) 3 use are restrictive. For the v2022.09 reference design, the peripherals have been shifted down, leaving more contiguous address space for their custom IP/peripherals. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-27riscv: dts: microchip: icicle: update pci address propertiesConor Dooley1-5/+5
For the v2022.09 reference design the PCI root port's data region has been moved to FIC1 from FIC0. This is a shorter path, allowing for higher clock rates and improved through-put. As a result, the address at which the PCIe's data region appears to the core complex has changed. The config region's address is unchanged. As FIC0 is no longer used, its clock can be removed too. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-27riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsiConor Dooley3-33/+58
In today's edition of moving things around: The PCIe root port on PolarFire SoC is more part of the FPGA than of the Core Complex. It is located on the other side of the chip and, apart from its interrupts, most of its configuration is determined by the FPGA bitstream rather. This includes: - address translation in both directions - the addresses at which the config and data regions appear to the core complex - the clocks used by the AXI bus - the plic interrupt used Moving the PCIe node to the -fabric.dtsi makes it clearer than a singular configuration for root port is not correct & allows the base SoC dtsi to be more easily included. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-27riscv: dts: microchip: add pci dma ranges for the icicle kitConor Dooley2-2/+8
The recently removed, accidentally included, "matr0" property was used in place of a dma-ranges property. The PCI controller is non-functional with mainline Linux in the v2022.02 or later reference designs and has not worked without configuration of address-translation since v2021.08. Add the address translation that will be used by the v2022.09 reference design & update the compatible used by the dts. Since this change is not backwards compatible, update the compatible to denote this, jumping over v2022.09 directly to v2022.10. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-20riscv: efi: enable generic EFI compressed bootArd Biesheuvel2-0/+7
Wire up the generic EFI zboot support for RISC-V. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-31riscv: dts: microchip: use an mpfs specific l2 compatibleConor Dooley1-1/+1
PolarFire SoC does not have the same l2 cache controller as the fu540, featuring an extra interrupt. Appease the devicetree checker overlords by adding a PolarFire SoC specific compatible to fix the below sort of warnings: mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts") Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-24riscv: dts: microchip: mpfs: remove pci axi address translation propertyConor Dooley1-1/+0
An AXI master address translation table property was inadvertently added to the device tree & this was not caught by dtbs_check at the time. Remove the property - it should not be in mpfs.dtsi anyway as it would be more suitable in -fabric.dtsi nor does it actually apply to the version of the reference design we are using for upstream. Link: https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide # Section 1.3.3 Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-24riscv: dts: microchip: mpfs: remove bogus card-detect-delayConor Dooley2-2/+0
Recent versions of dt-schema warn about a previously undetected undocumented property: arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: mmc@20008000: Unevaluated properties are not allowed ('card-detect-delay' was unexpected) From schema: Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml There are no GPIOs connected to MSSIO6B4 pin K3 so adding the common cd-debounce-delay-ms property makes no sense. The Cadence IP has a register that sets the card detect delay as "DP * tclk". On MPFS, this clock frequency is not configurable (it must be 200 MHz) & the FPGA comes out of reset with this register already set. Fixes: bc47b2217f24 ("riscv: dts: microchip: add the sundance polarberry") Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-24riscv: dts: microchip: mpfs: remove ti,fifo-depth propertyConor Dooley2-4/+0
Recent versions of dt-schema warn about a previously undetected undocument property on the icicle & polarberry devicetrees: arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: ethernet@20112000: ethernet-phy@8: Unevaluated properties are not allowed ('ti,fifo-depth' was unexpected) From schema: Documentation/devicetree/bindings/net/cdns,macb.yaml I know what you're thinking, the binding doesn't look to be the problem and I agree. I am not sure why a TI vendor property was ever actually added since it has no meaning... just get rid of it. Fixes: bc47b2217f24 ("riscv: dts: microchip: add the sundance polarberry") Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-24riscv: dts: microchip: mpfs: fix incorrect pcie child node nameConor Dooley1-1/+1
Recent versions of dt-schema complain about the PCIe controller's child node name: arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected) From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml Make the dts match the correct property name in the dts. Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-17riscv: dts: microchip: correct L2 cache interruptsHeinrich Schuchardt1-1/+1
The "PolarFire SoC MSS Technical Reference Manual" documents the following PLIC interrupts: 1 - L2 Cache Controller Signals when a metadata correction event occurs 2 - L2 Cache Controller Signals when an uncorrectable metadata event occurs 3 - L2 Cache Controller Signals when a data correction event occurs 4 - L2 Cache Controller Signals when an uncorrectable data event occurs This differs from the SiFive FU540 which only has three L2 cache related interrupts. The sequence in the device tree is defined by an enum: enum {         DIR_CORR = 0,         DATA_CORR,         DATA_UNCORR,         DIR_UNCORR, }; So the correct sequence of the L2 cache interrupts is interrupts = <1>, <3>, <4>, <2>; [Conor] This manifests as an unusable system if the l2-cache driver is enabled, as the wrong interrupt gets cleared & the handler prints errors to the console ad infinitum. Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") CC: stable@vger.kernel.org # 5.15: e35b07a7df9b: riscv: dts: microchip: mpfs: Group tuples in interrupt properties Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-15riscv: dts: microchip: add qspi compatible fallbackConor Dooley1-1/+1
The "hard" QSPI peripheral on PolarFire SoC is derived from version 2 of the FPGA IP core. The original binding had no fallback etc, so this device tree is valid as is. There was also no functional driver for the QSPI IP, so no device with a devicetree from a previous mainline release will regress. Link: https://lore.kernel.org/linux-spi/7c9f0d96-2882-964a-cd1f-916ddb3f0410@linaro.org/ Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-08-11riscv: dts: starfive: correct number of external interruptsMark Kettenis1-1/+1
The PLIC integrated on the Vic_U7_Core integrated on the StarFive JH7100 SoC actually supports 133 external interrupts. 127 of these are exposed to the outside world; the remainder are used by other devices that are part of the core-complex such as the L2 cache controller. But all 133 interrupts are external interrupts as far as the PLIC is concerned. Fix the property so that the driver can manage these additional interrupts, which is important since the interrupts for the L2 cache controller are enabled by default. Fixes: ec85362fb121 ("RISC-V: Add initial StarFive JH7100 device tree") Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220707185529.19509-1-kettenis@openbsd.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-08-11riscv: dts: sifive unmatched: Add PWM controlled LEDsEmil Renner Berthing1-0/+42
This adds the two PWM controlled LEDs to the HiFive Unmatched device tree. D12 is just a regular green diode, but D2 is an RGB diode with 3 PWM inputs controlling the three different colours. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Pavel Machek <pavel@ucw.cz> Tested-by: Ron Economos <re@w6rz.net> Link: https://lore.kernel.org/r/20220705210143.315151-5-emil.renner.berthing@canonical.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-08-11RISC-V: Canaan devicetree fixesPalmer Dabbelt7-31/+66
This series should rid us of dtbs_check errors for the RISC-V Canaan k210 based boards. To make keeping it that way a little easier, I changed the Canaan devicetree Makefile so that it would build all of the devicetrees in the directory if SOC_CANAAN. Link: https://lore.kernel.org/all/mhng-85044754-c361-40bc-a6a2-7082f35930bb@palmer-ri-x1c9/ * remotes/palmer/riscv-canaan_dt_schema: riscv: dts: canaan: build all devicetress if SOC_CANAAN riscv: dts: canaan: add specific compatible for kd233's LCD riscv: dts: canaan: fix bus {ranges,reg} warnings riscv: dts: canaan: remove spi-max-frequency from controllers riscv: dts: canaan: use custom compatible for k210 i2s riscv: dts: canaan: fix kd233 display spi frequency riscv: dts: canaan: fix mmc node names riscv: dts: canaan: fix the k210's timer nodes riscv: dts: canaan: fix the k210's memory node dt-bindings: memory-controllers: add canaan k210 sram controller dt-bindings: display: ili9341: document canaan kd233's lcd dt-bindings: display: convert ilitek,ili9341.txt to dt-schema
2022-08-07Merge tag 'riscv-for-linus-5.20-mw0' of ↵Linus Torvalds6-6/+99
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Enabling the FPU is now a static_key - Improvements to the Svpbmt support - CPU topology bindings for a handful of systems - Support for systems with 64-bit hart IDs - Many settings have been enabled in the defconfig, including both support for the StarFive systems and many of the Docker requirements There are also a handful of cleanups and improvements, as usual. * tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (28 commits) riscv: enable Docker requirements in defconfig riscv: convert the t-head pbmt errata to use the __nops macro riscv: introduce nops and __nops macros for NOP sequences RISC-V: Add fast call path of crash_kexec() riscv: mmap with PROT_WRITE but no PROT_READ is invalid riscv/efi_stub: Add 64bit boot-hartid support on RV64 riscv: cpu: Add 64bit hartid support on RV64 riscv: smp: Add 64bit hartid support on RV64 riscv: spinwait: Fix hartid variable type riscv: cpu_ops_sbi: Add 64bit hartid support on RV64 riscv: dts: sifive: "fix" pmic watchdog node name riscv: dts: canaan: Add k210 topology information riscv: dts: sifive: Add fu740 topology information riscv: dts: sifive: Add fu540 topology information riscv: dts: starfive: Add JH7100 CPU topology RISC-V: Add CONFIG_{NON,}PORTABLE riscv: config: enable SOC_STARFIVE in defconfig riscv: dts: microchip: Add mpfs' topology information riscv: Kconfig.socs: Add comments riscv: Kconfig.erratas: Add comments ...
2022-07-29Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski5-7/+7
No conflicts. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-07-21Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-0/+4
No conflicts. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-07-15riscv: dts: canaan: build all devicetress if SOC_CANAANConor Dooley1-2/+8
Testing & checking the Canaan devicetrees is inconvenient as only the devicetree corresponding to SOC_CANAAN_K210_DTB_BUILTIN will be built. Change the Makefile so that all devicetrees are built by default if SOC_CANAAN but only the one specified by SOC_CANAAN_K210_DTB_BUILTIN gets built as an object. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220705215213.1802496-14-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15riscv: dts: canaan: add specific compatible for kd233's LCDConor Dooley1-1/+1
Add the recently introduced compatible for the LCD on the Canaan KD233. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220705215213.1802496-13-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15riscv: dts: canaan: fix bus {ranges,reg} warningsConor Dooley1-3/+3
The k210 devicetrees warn about missing/empty reg and/or ranges properties: arch/riscv/boot/dts/canaan/k210.dtsi:408.22-460.5: Warning (unit_address_vs_reg): /soc/bus@52000000: node has a unit name, but no reg or ranges property arch/riscv/boot/dts/canaan/k210.dtsi:352.22-406.5: Warning (simple_bus_reg): /soc/bus@50400000: missing or empty reg/ranges property Add a ranges properties that naively caps the buses after the allocation of their last devices. Tested-by: Niklas Cassel <niklas.cassel@wdc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220705215213.1802496-12-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15riscv: dts: canaan: remove spi-max-frequency from controllersConor Dooley1-4/+1
spi-max-frequency is a device, not a controller property and should be removed. Link: https://lore.kernel.org/lkml/20220526014141.2872567-1-robh@kernel.org/ Tested-by: Niklas Cassel <niklas.cassel@wdc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220705215213.1802496-11-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15riscv: dts: canaan: use custom compatible for k210 i2sConor Dooley1-3/+3
The devicetrees using the Canaan k210 all have a sound-dai-cells value of 1, whereas the standard binding example for the DesignWare i2s and other use cases suggest 0. Use a k210 specific compatible which supports this difference. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220705215213.1802496-10-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15riscv: dts: canaan: fix kd233 display spi frequencyConor Dooley1-1/+1
The binding for the ili9341 specifies a const spi-max-frequency of 10 MHz but the kd233 devicetree entry has it listed at 15 Mhz. Align the devicetree with the value in the binding. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220705215213.1802496-9-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15riscv: dts: canaan: fix mmc node namesConor Dooley5-5/+5
The newly-converted-to-dt-schema binding expects the mmc node name to be '^mmc(@.*)?$' so align the devicetree with the schema. Tested-by: Niklas Cassel <niklas.cassel@wdc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220705215213.1802496-8-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15riscv: dts: canaan: fix the k210's timer nodesConor Dooley1-8/+38
The timers on the k210 have non standard interrupt configurations, which leads to dtbs_check warnings: k210_generic.dtb: timer@502d0000: interrupts: [[14], [15]] is too long From schema: Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml Split the timer nodes in two, so that the second timer in the IP block can actually be accessed & in the process solve the dtbs_check warning. Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220705215213.1802496-7-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15riscv: dts: canaan: fix the k210's memory nodeConor Dooley1-4/+6
The k210 U-Boot port has been using the clocks defined in the devicetree to bring up the board's SRAM, but this violates the dt-schema. As such, move the clocks to a dedicated node with the same compatible string. The regs property does not fit in either node, so is replaced by comments. Tested-by: Niklas Cassel <niklas.cassel@wdc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220705215213.1802496-6-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15riscv: dts: sifive: "fix" pmic watchdog node nameConor Dooley1-1/+1
After converting the pmic watchdog binding to yaml, dtbs_check complains that the node name doesn't match the binding. "Fix" it. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220606201343.514391-5-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15Merge branch 'riscv-cpu_map_topo' of ↵Palmer Dabbelt4-2/+74
git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git into for-next RISC-V: Add cpu-map topology information nodes It was reported to me that the Hive Unmatched incorrectly reports its topology to hwloc, but the StarFive VisionFive did in [0] & a subsequent off-list email from Brice (the hwloc maintainer). This turned out not to be entirely true, the /downstream/ version of the VisionFive does work correctly but not upstream, as the downstream devicetree has a cpu-map node that was added recently. This series adds a cpu-map node to all upstream devicetrees, which I have tested on mpfs & fu540. The first patch is lifted directly from the downstream StarFive devicetree. 0: https://github.com/open-mpi/hwloc/issues/536 Link: https://lore.kernel.org/linux-riscv/20220705190435.1790466-1-mail@conchuod.ie/ [Palmer: except the Microchip DT, that went in via the previous PR.] * 'riscv-cpu_map_topo' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git: riscv: dts: canaan: Add k210 topology information riscv: dts: sifive: Add fu740 topology information riscv: dts: sifive: Add fu540 topology information riscv: dts: starfive: Add JH7100 CPU topology
2022-07-15riscv: dts: canaan: Add k210 topology informationConor Dooley1-0/+12
The k210 has no cpu-map node, so tools like hwloc cannot correctly parse the topology. Add the node using the existing node labels. Reported-by: Brice Goglin <Brice.Goglin@inria.fr> Link: https://github.com/open-mpi/hwloc/issues/536 Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Link: https://lore.kernel.org/r/20220705190435.1790466-6-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15riscv: dts: sifive: Add fu740 topology informationConor Dooley1-0/+24
The fu740 has no cpu-map node, so tools like hwloc cannot correctly parse the topology. Add the node using the existing node labels. Reported-by: Brice Goglin <Brice.Goglin@inria.fr> Link: https://github.com/open-mpi/hwloc/issues/536 Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220705190435.1790466-4-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15riscv: dts: sifive: Add fu540 topology informationConor Dooley1-0/+24
The fu540 has no cpu-map node, so tools like hwloc cannot correctly parse the topology. Add the node using the existing node labels. Reported-by: Brice Goglin <Brice.Goglin@inria.fr> Link: https://github.com/open-mpi/hwloc/issues/536 Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220705190435.1790466-3-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15riscv: dts: starfive: Add JH7100 CPU topologyJonas Hahnfeld1-2/+14
Add cpu-map binding to inform the kernel about the hardware topology of the CPU cores. Before this change, lstopo would report 1 core with 2 threads: Machine (7231MB total) Package L#0 NUMANode L#0 (P#0 7231MB) L2 L#0 (2048KB) + Core L#0 L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0) L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1) After this change, it correctly identifies two cores: Machine (7231MB total) Package L#0 NUMANode L#0 (P#0 7231MB) L2 L#0 (2048KB) L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0) L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1) Signed-off-by: Jonas Hahnfeld <hahnjo@hahnjo.de> Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220705190435.1790466-2-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-15riscv: dts: align gpio-key node names with dtschemaKrzysztof Kozlowski5-7/+7
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220624170811.66395-1-krzysztof.kozlowski@linaro.org Link: https://lore.kernel.org/all/20220616005224.18391-1-krzysztof.kozlowski@linaro.org/ Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-08riscv: dts: microchip: Add mpfs' topology informationConor Dooley1-0/+24
The mpfs has no cpu-map node, so tools like hwloc cannot correctly parse the topology. Add the node using the existing node labels. Reported-by: Brice Goglin <Brice.Goglin@inria.fr> Link: https://github.com/open-mpi/hwloc/issues/536 Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
2022-07-05riscv: dts: microchip: hook up the mpfs' l2cacheConor Dooley1-0/+4
The initial PolarFire SoC devicetree must have been forked off from the fu540 one prior to the addition of l2cache controller support being added there. When the controller node was added to mpfs.dtsi, it was not hooked up to the CPUs & thus sysfs reports an incorrect cache configuration. Hook it up. Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-06-27Merge tag 'linux-can-next-for-5.20-20220625' of ↵David S. Miller1-0/+18
git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next Marc Kleine-Budde says: ==================== pull-request: can-next 2022-06-25 this is a pull request of 22 patches for net-next/master. The first 2 patches target the xilinx driver. Srinivas Neeli's patch adds Transmitter Delay Compensation (TDC) support, a patch by me fixes a typo. The next patch is by me and fixes a typo in the m_can driver. Another patch by me allows the configuration of fixed bit rates without need for do_set_bittiming callback. The following 7 patches are by Vincent Mailhol and refactor the can-dev module and Kbuild, de-inline the can_dropped_invalid_skb() function, which has grown over the time, and drop outgoing skbs if the controller is in listen only mode. Max Staudt's patch fixes a reference in the networking/can.rst documentation. Vincent Mailhol provides 2 patches with cleanups for the etas_es58x driver. Conor Dooley adds bindings for the mpfs-can to the PolarFire SoC dtsi. Another patch by me allows the configuration of fixed data bit rates without need for do_set_data_bittiming callback. The last 5 patches are by Frank Jungclaus. They prepare the esd_usb driver to add support for the the CAN-USB/3 device in a later series. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-16riscv: dts: microchip: remove spi-max-frequency propertyNagasuresh Relli1-1/+0
Remove the spi-max-frequency property from the spi0 controller node as it is supposed to be a per SPI peripheral device property. Reported-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/lkml/20220526014141.2872567-1-robh@kernel.org/ Signed-off-by: Nagasuresh Relli <nagasuresh.relli@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-06-13riscv: dts: microchip: add mpfs's CAN controllersConor Dooley1-0/+18
PolarFire SoC has a pair of CAN controllers, but as they were undocumented there were omitted from the device tree. Add them. Link: https://lore.kernel.org/all/20220607065459.2035746-3-conor.dooley@microchip.com Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-06-12riscv: dts: microchip: re-add pdma to mpfs device treeConor Dooley1-0/+9
PolarFire SoC /does/ have a SiFive pdma, despite what I suggested as a conflict resolution to Zong. Somehow the entry fell through the cracks between versions of my dt patches, so re-add it with Zong's updated compatible & dma-channels property. Fixes: c5094f371008 ("riscv: dts: microchip: refactor icicle kit device tree") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-06-06riscv: dts: microchip: remove spi-max-frequency propertyConor Dooley1-2/+0
spi-max-frequency property is supposed to be a per SPI peripheral device property, not a SPI controller property, so remove it. Reported-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/lkml/20220526014141.2872567-1-robh@kernel.org/ Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-06-02riscv: dts: icicle: sort nodes alphabeticallyConor Dooley1-52/+52
The icicle device tree is in a "random" order, so clean it up and sort its elements alphabetically to match the newly added PolarBerry dts. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220509142610.128590-11-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-02riscv: microchip: icicle: readability fixesConor Dooley1-3/+5
Fix the sort order of the status properties, remove some extra whitespace in the mmc entry & add whitespace to the mac entry containing the phys so that the dt is easier to read. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220509142610.128590-10-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-02riscv: dts: microchip: add the sundance polarberryConor Dooley3-0/+116
Add a minimal device tree for the PolarFire SoC based Sundance PolarBerry. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220509142610.128590-9-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-02riscv: dts: microchip: make the fabric dtsi board specificConor Dooley3-1/+3
Currently mpfs-fabric.dtsi is included by mpfs.dtsi - which is fine currently since there is only one board with this SoC upstream. However if another board was added, it would include the fabric contents of the Icicle Kit's reference design. To avoid this, rename mpfs-fabric.dtsi to mpfs-icicle-kit-fabric.dtsi & include it in the dts rather than mpfs.dtsi. mpfs-icicle-kit-fabric.dtsi specifically matches the 22.03 reference design for the icicle kit's FPGA fabric & an older version of the design may not have the i2c or pwm devices - so add the compatible string to document this. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220509142610.128590-6-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-02riscv: dts: microchip: remove soc vendor from filenamesConor Dooley4-3/+3
Having the SoC vendor both as the directory and in the filename adds little. Remove microchip from the filenames so that the files will resemble the other directories in riscv (and arm64). The new names follow a soc-board.dts & soc{,-fabric}.dtsi pattern. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220509142610.128590-4-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-02riscv: dts: microchip: move sysctrlr out of soc busConor Dooley1-5/+5
The MPFS system controller has no registers of its own, so move it out of the soc node to avoid dtbs_check warnings: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontroller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]], 'status': ['okay']} should not be valid under {'type': 'object'} Reported-by: Palmer Dabbelt <palmer@rivosinc.com> Suggested-by: Rob Herring <robh@kernel.org> Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220509142610.128590-3-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-02riscv: dts: microchip: remove icicle memory clocksConor Dooley1-2/+0
The clock properties in the icicle kit's memory entries cause dtbs_check errors: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: /: memory@80000000: 'clocks' does not match any of the regexes: 'pinctrl-[0-9]+' Get rid of the clocks to avoid the errors. Reported-by: Palmer Dabbelt <palmer@rivosinc.com> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Fixes: 5b28df37d311 ("riscv: dts: microchip: update peripherals in icicle kit device tree") Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220509142610.128590-2-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01Merge tag 'riscv-for-linus-5.19-mw0' of ↵Linus Torvalds2-1/+3
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for the Svpbmt extension, which allows memory attributes to be encoded in pages - Support for the Allwinner D1's implementation of page-based memory attributes - Support for running rv32 binaries on rv64 systems, via the compat subsystem - Support for kexec_file() - Support for the new generic ticket-based spinlocks, which allows us to also move to qrwlock. These should have already gone in through the asm-geneic tree as well - A handful of cleanups and fixes, include some larger ones around atomics and XIP * tag 'riscv-for-linus-5.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (51 commits) RISC-V: Prepare dropping week attribute from arch_kexec_apply_relocations[_add] riscv: compat: Using seperated vdso_maps for compat_vdso_info RISC-V: Fix the XIP build RISC-V: Split out the XIP fixups into their own file RISC-V: ignore xipImage RISC-V: Avoid empty create_*_mapping definitions riscv: Don't output a bogus mmu-type on a no MMU kernel riscv: atomic: Add custom conditional atomic operation implementation riscv: atomic: Optimize dec_if_positive functions riscv: atomic: Cleanup unnecessary definition RISC-V: Load purgatory in kexec_file RISC-V: Add purgatory RISC-V: Support for kexec_file on panic RISC-V: Add kexec_file support RISC-V: use memcpy for kexec_file mode kexec_file: Fix kexec_file.c build error for riscv platform riscv: compat: Add COMPAT Kbuild skeletal support riscv: compat: ptrace: Add compat_arch_ptrace implement riscv: compat: signal: Add rt_frame implementation riscv: add memory-type errata for T-Head ...
2022-05-27RISC-V: Various XIP fixesPalmer Dabbelt1-0/+1
This fixes a handful of issues with the XIP support, which has bit rotted some lately. * palmer/riscv-xip: RISC-V: Fix the XIP build RISC-V: Split out the XIP fixups into their own file RISC-V: ignore xipImage RISC-V: Avoid empty create_*_mapping definitions
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