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2024-05-23riscv: make image compression configurableEmil Renner Berthing1-3/+6
Previously the build process would always set KBUILD_IMAGE to the uncompressed Image file (unless XIP_KERNEL or EFI_ZBOOT was enabled) and unconditionally compress it into Image.gz. However there are already build targets for Image.bz2, Image.lz4, Image.lzma, Image.lzo and Image.zstd, so let's make use of those, make the compression method configurable and set KBUILD_IMAGE accordingly so that targets like 'make install' and 'make bindeb-pkg' will use the chosen image. Tested-by: Björn Töpel <bjorn@rivosinc.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Nicolas Schier <n.schier@avm.de> Reviewed-by: Masahiro Yamada <masahiroy@kernel.org> Link: https://lore.kernel.org/r/20240504193446.196886-2-emil.renner.berthing@canonical.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-05-21Merge tag 'soc-dt-late-6.10' of ↵Linus Torvalds8-711/+692
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull more SoC devicetree updates from Arnd Bergmann: "This is a follow-up to an earlier pull request for device tree changes, as three platform maintainers sent their contents too late to be included in the main set, but had not caused any further problems since then: - The Amlogic platform now containts support for two new SoC types, the A4 and A5 chips for audio applications. Both come with a reference board, and one more dts file gets addded for the combination of the MNT Reform Laptop with the BPI-CM4 CPU module - The ASpeed platform adds support for six addititional server platforms that use ast2500 or ast2600 as their BMC, while another one gets removed - The RISC-V platforms from Microchip, Starfive and and T-HEAD get additional features for existing hardware, plus the addition of the Milk-V Mars based on the StarFive VisionFive v2 board" * tag 'soc-dt-late-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (76 commits) riscv: dts: microchip: add pac1934 power-monitor to icicle riscv: dts: thead: Fix node ordering in TH1520 device tree ARM: dts: aspeed: Add ASRock E3C256D4I BMC dt-bindings: arm: aspeed: document ASRock E3C256D4I dt-bindings: trivial-devices: add isil,isl69269 ARM: dts: aspeed: x4tf: Add dts for asus x4tf project dt-bindings: arm: aspeed: add ASUS X4TF board ARM: dts: aspeed: Remove Facebook Cloudripper dts ARM: dts: aspeed: drop unused ref_voltage ADC property ARM: dts: aspeed: harma: correct Mellanox multi-host property ARM: dts: aspeed: yosemitev2: correct Mellanox multi-host property ARM: dts: aspeed: yosemite4: correct Mellanox multi-host property ARM: dts: aspeed: greatlakes: correct Mellanox multi-host property ARM: dts: aspeed: Modify I2C bus configuration ARM: dts: aspeed: Disable unused ADC channels for Asrock X570D4U BMC ARM: dts: aspeed: Modify GPIO table for Asrock X570D4U BMC ARM: dts: aspeed: yosemite4: set bus13 frequency to 100k ARM: dts: Aspeed: Bonnell: Fix NVMe LED labels ARM: dts: aspeed: yosemite4: Enable ipmb device for OCP debug card ARM: dts: aspeed: ahe50dc: Update lm25066 regulator name ...
2024-05-18Merge tag 'kbuild-v6.10' of ↵Linus Torvalds1-2/+0
git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild Pull Kbuild updates from Masahiro Yamada: - Avoid 'constexpr', which is a keyword in C23 - Allow 'dtbs_check' and 'dt_compatible_check' run independently of 'dt_binding_check' - Fix weak references to avoid GOT entries in position-independent code generation - Convert the last use of 'optional' property in arch/sh/Kconfig - Remove support for the 'optional' property in Kconfig - Remove support for Clang's ThinLTO caching, which does not work with the .incbin directive - Change the semantics of $(src) so it always points to the source directory, which fixes Makefile inconsistencies between upstream and downstream - Fix 'make tar-pkg' for RISC-V to produce a consistent package - Provide reasonable default coverage for objtool, sanitizers, and profilers - Remove redundant OBJECT_FILES_NON_STANDARD, KASAN_SANITIZE, etc. - Remove the last use of tristate choice in drivers/rapidio/Kconfig - Various cleanups and fixes in Kconfig * tag 'kbuild-v6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild: (46 commits) kconfig: use sym_get_choice_menu() in sym_check_prop() rapidio: remove choice for enumeration kconfig: lxdialog: remove initialization with A_NORMAL kconfig: m/nconf: merge two item_add_str() calls kconfig: m/nconf: remove dead code to display value of bool choice kconfig: m/nconf: remove dead code to display children of choice members kconfig: gconf: show checkbox for choice correctly kbuild: use GCOV_PROFILE and KCSAN_SANITIZE in scripts/Makefile.modfinal Makefile: remove redundant tool coverage variables kbuild: provide reasonable defaults for tool coverage modules: Drop the .export_symbol section from the final modules kconfig: use menu_list_for_each_sym() in sym_check_choice_deps() kconfig: use sym_get_choice_menu() in conf_write_defconfig() kconfig: add sym_get_choice_menu() helper kconfig: turn defaults and additional prompt for choice members into error kconfig: turn missing prompt for choice members into error kconfig: turn conf_choice() into void function kconfig: use linked list in sym_set_changed() kconfig: gconf: use MENU_CHANGED instead of SYMBOL_CHANGED kconfig: gconf: remove debug code ...
2024-05-14Makefile: remove redundant tool coverage variablesMasahiro Yamada1-2/+0
Now Kbuild provides reasonable defaults for objtool, sanitizers, and profilers. Remove redundant variables. Note: This commit changes the coverage for some objects: - include arch/mips/vdso/vdso-image.o into UBSAN, GCOV, KCOV - include arch/sparc/vdso/vdso-image-*.o into UBSAN - include arch/sparc/vdso/vma.o into UBSAN - include arch/x86/entry/vdso/extable.o into KASAN, KCSAN, UBSAN, GCOV, KCOV - include arch/x86/entry/vdso/vdso-image-*.o into KASAN, KCSAN, UBSAN, GCOV, KCOV - include arch/x86/entry/vdso/vdso32-setup.o into KASAN, KCSAN, UBSAN, GCOV, KCOV - include arch/x86/entry/vdso/vma.o into GCOV, KCOV - include arch/x86/um/vdso/vma.o into KASAN, GCOV, KCOV I believe these are positive effects because all of them are kernel space objects. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Kees Cook <keescook@chromium.org> Tested-by: Roberto Sassu <roberto.sassu@huawei.com>
2024-05-07riscv: dts: microchip: add pac1934 power-monitor to icicleConor Dooley1-0/+32
The binding for this landed in v6.9, add the description. In the off-chance that there were people carrying local patches for this based on the driver shipped on the Microchip website (or vendor kernel) both the binding and sysfs filenames changed during upstreaming. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-05-07RISC-V: add Milkv Mars board devicetreeConor Dooley6-684/+633
The Milkv Mars is a development board based on the Starfive JH7110 SoC. The board features: - JH7110 SoC - 1/2/4/8 GiB LPDDR4 DRAM - AXP15060 PMIC - 40 pin GPIO header - 3x USB 3.0 host port - 1x USB 2.0 host port - 1x M.2 E-Key - 1x eMMC slot - 1x MicroSD slot - 1x QSPI Flash - 1x 1Gbps Ethernet port - 1x HDMI port - 1x 2-lane DSI and 1x 4-lane DSI - 1x 2-lane CSI I fixed up some nits Emil pointed out. This merges fixes into for-next to avoid messing around with some nodes that were removed as fixes this cycle. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-05-07riscv: dts: thead: Fix node ordering in TH1520 device treeThomas Bonnefille1-27/+27
According to the device tree coding style, nodes shall be ordered by unit address in ascending order. Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-05-02Merge tag 'riscv-sophgo-dt-for-v6.10' of https://github.com/sophgo/linux ↵Arnd Bergmann4-8/+157
into soc/dt RISC-V Devicetrees for v6.10 Sophgo: Added sdhci support for cv18xx/duo. Added clock support for cv18xx. Added clock for uart/sdhci. Added spi support for cv18xx. Added i2c support for cv18xx. Added reserved memory node for cv1800b/duo. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'riscv-sophgo-dt-for-v6.10' of https://github.com/sophgo/linux: riscv: dts: sophgo: add reserved memory node for CV1800B riscv: dts: sophgo: use real clock for sdhci riscv: dts: sophgo: cv18xx: Add i2c devices riscv: dts: sophgo: cv18xx: Add spi devices riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC riscv: dts: sophgo: add sdcard support for milkv duo Link: https://lore.kernel.org/r/MA0P287MB2822CA2DE757787D6EA3B1F8FE192@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-05-01riscv: dts: starfive: add Milkv Mars board device treeJisheng Zhang2-0/+31
The Milkv Mars is a development board based on the Starfive JH7110 SoC. The board features: - JH7110 SoC - 1/2/4/8 GiB LPDDR4 DRAM - AXP15060 PMIC - 40 pin GPIO header - 3x USB 3.0 host port - 1x USB 2.0 host port - 1x M.2 E-Key - 1x eMMC slot - 1x MicroSD slot - 1x QSPI Flash - 1x 1Gbps Ethernet port - 1x HDMI port - 1x 2-lane DSI and 1x 4-lane DSI - 1x 2-lane CSI Add the devicetree file describing the currently supported features, namely PMIC, UART, I2C, GPIO, SD card, QSPI Flash, eMMC and Ethernet. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-05-01riscv: dts: starfive: introduce a common board dtsi for jh7110 based boardsJisheng Zhang2-584/+600
This is to prepare for Milkv Mars board dts support in the following patch. Let's factored out common part into .dtsi. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-05-01riscv: dts: starfive: visionfive 2: add "disable-wp" for tfcardJisheng Zhang1-0/+1
No physical write-protect line is present, so setting "disable-wp". Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-05-01riscv: dts: starfive: visionfive 2: add tf cd-gpiosJisheng Zhang1-1/+1
Per VisionFive 2 1.2B, and 1.3A boards' SCH, GPIO 41 is used as card detect. So add "cd-gpios" property for this. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-05-01riscv: dts: starfive: visionfive 2: use cpus label for timebase freqJisheng Zhang1-4/+4
As pointed out by Krzysztof "Board should not bring new CPU nodes. Override by label instead." Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-05-01riscv: dts: starfive: visionfive 2: update sound and codec dt node nameJisheng Zhang1-2/+2
Use "audio-codec" as the codec dt node name, and "sound" as the simple audio card dt name. Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-05-01riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsiJisheng Zhang2-2/+2
Add the 'cpus' label so that we can reference it in board dts files. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-04-23riscv: dts: sophgo: add reserved memory node for CV1800BInochi Amaoto2-3/+14
The original dts of CV1800B has a weird memory length as it contains reserved memory for coprocessor. Make this area a separate node so it can get the real memory length. Link: https://lore.kernel.org/r/IA1PR20MB49531F274753B04A5547DB59BB052@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-04-22riscv: dts: renesas: rzfive-smarc-som: Drop deleting interrupt properties ↵Lad Prabhakar1-16/+0
from ETH0/1 nodes Now that we have enabled IRQC support for RZ/Five SoC switch to interrupt mode for ethernet0/1 PHYs instead of polling mode. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240403203503.634465-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-04-22riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSILad Prabhakar1-0/+75
Add the IRQC node to RZ/Five (R9A07G043F) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240403203503.634465-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-04-22riscv: dts: sophgo: use real clock for sdhciInochi Amaoto1-9/+3
As the clk patch is merged, Use real clocks for sdhci0. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/IA1PR20MB4953CA5D46EA8913B130D502BB052@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-04-15riscv: dts: starfive: visionfive 2: Remove non-existing I2S hardwareHannah Peuckmann1-58/+0
This partially reverts commit 92cfc35838b2 ("riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1") This added device tree nodes for I2S hardware that is not actually on the VisionFive 2 board, but connected on the 40pin header. Many different extension boards could be added on those pins, so this should be handled by overlays instead. This also conflicts with the TDM node which also attempts to grab GPIO 44: starfive-jh7110-sys-pinctrl 13040000.pinctrl: pin GPIO44 already requested by 10090000.tdm; cannot claim for 120c0000.i2s Fixes: 92cfc35838b2 ("riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1") Signed-off-by: Hannah Peuckmann <hannah.peuckmann@canonical.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-04-15riscv: dts: starfive: visionfive 2: Remove non-existing TDM hardwareHannah Peuckmann1-40/+0
This partially reverts commit e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm") This added device tree nodes for TDM hardware that is not actually on the VisionFive 2 board, but connected on the 40pin header. Many different extension boards could be added on those pins, so this should be handled by overlays instead. This also conflicts with the I2S node which also attempts to grab GPIO 44: starfive-jh7110-sys-pinctrl 13040000.pinctrl: pin GPIO44 already requested by 10090000.tdm; cannot claim for 120c0000.i2s Fixes: e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm") Signed-off-by: Hannah Peuckmann <hannah.peuckmann@canonical.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-04-11riscv: dts: sophgo: cv18xx: Add i2c devicesInochi Amaoto1-0/+55
Add i2c devices for the CV180x, CV181x and SG200x soc. Link: https://lore.kernel.org/r/IA1PR20MB49531AA2DBD4832B7926D4A8BB442@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-04-11riscv: dts: sophgo: cv18xx: Add spi devicesInochi Amaoto1-0/+44
Add spi devices for the CV180x, CV181x and SG200x soc. Link: https://lore.kernel.org/r/IA1PR20MB49532705DE532BCF81CCEFD0BB442@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-04-11riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoCInochi Amaoto1-5/+11
Add missing clocks of uart node for CV1800B and CV1812H. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/IA1PR20MB4953198222C3ABC2A2B6DE21BB262@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-04-11riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoCInochi Amaoto3-0/+14
Add clock generator node for CV1800B and CV1812H. Until now, It uses DT override to minimize duplication. This may change in the future. See the last link for the discussion on maintaining DT of CV1800 series. Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf Link: https://lore.kernel.org/all/IA1PR20MB495373158F3B690EF3BF2901BB8BA@IA1PR20MB4953.namprd20.prod.outlook.com/ Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/IA1PR20MB4953ED6A4B57773865F49D6DBB262@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-03-27riscv: dts: sophgo: add sdcard support for milkv duoJisheng Zhang2-0/+25
Add sdhci dt node in SoC dtsi and enable it in milkv duo dts. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Inochi Amaoto <inochiama@outlook.com> Link: https://lore.kernel.org/r/20240217144826.3944-1-jszhang@kernel.org Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-03-27riscv: dts: starfive: Remove PMIC interrupt info for Visionfive 2 boardShengyu Qu1-1/+0
Interrupt line number of the AXP15060 PMIC is not a necessary part of its device tree. Originally the binding required one, so the dts patch added an invalid interrupt that the driver ignored (0) as the interrupt line of the PMIC is not actually connected on this platform. This went unnoticed during review as it would have been a valid interrupt for a GPIO controller, but it is not for the PLIC. The PLIC, on this platform at least, silently ignores the enablement of interrupt 0. Bo Gan is running a modified version of OpenSBI that faults if writes are done to reserved fields, so their kernel runs into problems. Delete the invalid interrupt from the device tree. Cc: stable@vger.kernel.org Reported-by: Bo Gan <ganboing@gmail.com> Link: https://lore.kernel.org/all/c8b6e960-2459-130f-e4e4-7c9c2ebaa6d3@gmail.com/ Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Fixes: 2378341504de ("riscv: dts: starfive: Enable axp15060 pmic for cpufreq") [conor: rewrite the commit message to add more detail] Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-22Merge tag 'riscv-for-linus-6.9-mw2' of ↵Linus Torvalds1-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for various vector-accelerated crypto routines - Hibernation is now enabled for portable kernel builds - mmap_rnd_bits_max is larger on systems with larger VAs - Support for fast GUP - Support for membarrier-based instruction cache synchronization - Support for the Andes hart-level interrupt controller and PMU - Some cleanups around unaligned access speed probing and Kconfig settings - Support for ACPI LPI and CPPC - Various cleanus related to barriers - A handful of fixes * tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (66 commits) riscv: Fix syscall wrapper for >word-size arguments crypto: riscv - add vector crypto accelerated AES-CBC-CTS crypto: riscv - parallelize AES-CBC decryption riscv: Only flush the mm icache when setting an exec pte riscv: Use kcalloc() instead of kzalloc() riscv/barrier: Add missing space after ',' riscv/barrier: Consolidate fence definitions riscv/barrier: Define RISCV_FULL_BARRIER riscv/barrier: Define __{mb,rmb,wmb} RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ cpufreq: Move CPPC configs to common Kconfig and add RISC-V ACPI: RISC-V: Add CPPC driver ACPI: Enable ACPI_PROCESSOR for RISC-V ACPI: RISC-V: Add LPI driver cpuidle: RISC-V: Move few functions to arch/riscv riscv: Introduce set_compat_task() in asm/compat.h riscv: Introduce is_compat_thread() into compat.h riscv: add compile-time test into is_compat_task() riscv: Replace direct thread flag check with is_compat_task() riscv: Improve arch_get_mmap_end() macro ...
2024-03-19Merge tag 'soc-late-6.9' of ↵Linus Torvalds7-4/+335
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull more ARM SoC updates from Arnd Bergmann: "These are changes that for some reason ended up not making it into the first four branches but that should still make it into 6.9: - A rework of the omap clock support that touches both drivers and device tree files - The reset controller branch changes that had a dependency on late bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the drivers branch - The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree changes that got delayed and needed some extra time in linux-next for wider testing" * tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (31 commits) soc: fsl: dpio: fix kcalloc() argument order bus: ts-nbus: Improve error reporting bus: ts-nbus: Convert to atomic pwm API riscv: dts: starfive: jh7110: Add camera subsystem nodes ARM: bcm: stop selecing CONFIG_TICK_ONESHOT ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift clk: ti: Improve clksel clock bit parsing for reg property clk: ti: Handle possible address in the node name dt-bindings: pwm: opencores: Add compatible for StarFive JH8100 dt-bindings: riscv: cpus: reg matches hart ID reset: Instantiate reset GPIO controller for shared reset-gpios reset: gpio: Add GPIO-based reset controller cpufreq: do not open-code of_phandle_args_equal() of: Add of_phandle_args_equal() helper reset: simple: add support for Sophgo SG2042 dt-bindings: reset: sophgo: support SG2042 riscv: dts: microchip: add specific compatible for mpfs pdma riscv: dts: microchip: add missing CAN bus clocks ARM: brcmstb: Add debug UART entry for 74165 ...
2024-03-14Merge tag 'pinctrl-v6.9-1' of ↵Linus Torvalds1-0/+4
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "No core changes this time around. New drivers: - New driver for Renesas R8A779H0 also known as R-Car V4M. - New driver for the Awinic AW9523/B I2C GPIO expander. I found this living out-of-tree in OpenWrt as an upstream attempt had stalled on the finishing line, so I picked it up and finished the job. Improvements: - The Nomadik pin control driver was for years re-used out of tree for the ST STA chips, and now the IP was re-used in a MIPS automotive SoC called MobilEyeq5, so it has been split in pin control and GPIO drivers so the latter can be reused by MobilEyeq5. (Along with a long list of cleanups) - A lot of overall cleanup and tidying up" * tag 'pinctrl-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (87 commits) drivers/gpio/nomadik: move dummy nmk_gpio_dbg_show_one() to header gpio: nomadik: remove BUG_ON() in nmk_gpio_populate_chip() dt-bindings: pinctrl: qcom: update compatible name for match with driver pinctrl: aw9523: Make the driver tristate pinctrl: nomadik: fix dereference of error pointer gpio: nomadik: Back out some managed resources pinctrl: aw9523: Add proper terminator pinctrl: core: comment that pinctrl_add_gpio_range() is deprecated pinctrl: pinmux: Suppress error message for -EPROBE_DEFER pinctrl: Add driver for Awinic AW9523/B I2C GPIO Expander dt-bindings: pinctrl: Add bindings for Awinic AW9523/AW9523B gpio: nomadik: Finish conversion to use firmware node APIs gpio: nomadik: fix Kconfig dependencies inbetween pinctrl & GPIO pinctrl: da9062: Add OF table dt-bindings: pinctrl: at91: add sam9x7 pinctrl: ocelot: remove redundant assignment to variable ret gpio: nomadik: grab optional reset control and deassert it at probe gpio: nomadik: support mobileye,eyeq5-gpio gpio: nomadik: handle variadic GPIO count gpio: nomadik: support shared GPIO IRQs ...
2024-03-12riscv: dts: renesas: Add Andes PMU extension for r9a07g043fYu Chien Peter Lin1-1/+1
xandespmu stands for Andes Performance Monitor Unit extension. Based on the added Andes PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240222083946.3977135-10-peterlin@andestech.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-03-12riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTCYu Chien Peter Lin1-1/+1
The Andes hart-level interrupt controller (Andes INTC) allows AX45MP cores to handle custom local interrupts, such as the performance counter overflow interrupt. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240222083946.3977135-6-peterlin@andestech.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-03-11Merge tag 'riscv-dt-fixes-for-v6.8-final' of ↵Arnd Bergmann5-5/+5
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetree fixes for v6.8-final Starfive: The previous cleanup broke boot on the jh7100 as the driver depended on the fallback clock name created based on the node-name when clock-output-names is not present. Add clock-output-names to restore working order. Generic: BUILTIN_DTB has been broken for ages on any platform other than the nommu Canaan k210 SoC as the first dtb built (in alphanumerical order), would get built into the image. This didn't get fixed for ages because nobody actually cared about running it other than the k210 enough to fix it. The folks doing Sophgo SG2042 development have come along and fixed it, as they want to use builtin dtbs. linux-boot on that platform reuses the dtb it was provided by OpenSBI when booting linux proper, which is unfortunately not possible to boot a mainline kernel with. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-fixes-for-v6.8-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: Move BUILTIN_DTB_SOURCE to common Kconfig riscv: dts: starfive: jh7100: fix root clock names Link: https://lore.kernel.org/r/20240306-waltz-facial-9e4e1b792053@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-03-06Merge tag 'riscv-dt-for-v6.9' of ↵Arnd Bergmann7-4/+335
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/late RISC-V Devicetrees for v6.9 Microchip: Missing bus clocks for the CAN controllers spotted during the creation of a driver for the controllers and a specific compatible for the SiFive PDMA block on PolarFire SoC. Starfive: PWM nodes for the jh7100 and jh7110. Camera subsystem support for the latter. Most notably however is the addition of ethernet support for the jh7110 which finally allows people to use the network on the OG VisionFive and on the Beagle-V Starlight board. This was made possible by the non-standard cache management operations support added for the RZ/Five which could be extended to the ccache present on the jh7100. bindings: Additional clarification for what the reg property represents for cpus and two opencores PWM binding changes - the original addition and an added compatible. The latter is here as the driver patch was not ready but the PWM maintainer told me to go ahead and merge it. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: jh7110: Add camera subsystem nodes dt-bindings: pwm: opencores: Add compatible for StarFive JH8100 dt-bindings: riscv: cpus: reg matches hart ID riscv: dts: microchip: add specific compatible for mpfs pdma riscv: dts: microchip: add missing CAN bus clocks riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio riscv: dts: starfive: visionfive-v1: Setup ethernet phy riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes riscv: dts: starfive: jh7110: Add PWM node and pins configuration riscv: dts: starfive: jh7100: Add PWM node and pins configuration dt-bindings: pwm: Add bindings for OpenCores PWM Controller Link: https://lore.kernel.org/r/20240305-iodine-moneywise-53797ae9bf6e@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-03-06riscv: dts: Move BUILTIN_DTB_SOURCE to common KconfigYangyu Chen4-5/+1
The BUILTIN_DTB_SOURCE was only configured for K210 before. Since SOC_BUILTIN_DTB_DECLARE was removed at commit d5805af9fe9f ("riscv: Fix builtin DTB handling") from patch [1], the kernel cannot choose one of the dtbs from then on and always take the first one dtb to use. Then, another commit 0ddd7eaffa64 ("riscv: Fix BUILTIN_DTB for sifive and microchip soc") from patch [2] supports BUILTIN_DTB_SOURCE for other SoCs. However, this feature will only work if the Kconfig we use links the dtb we expected in the first place as mentioned in the thread [3]. Thus, a config BUILTIN_DTB_SOURCE is needed for all SoCs to choose one dtb to use. For some considerations, this patch also removes default y if XIP_KERNEL for BUILTIN_DTB, as this requires setting a proper dtb to use on the BUILTIN_DTB_SOURCE, else the kernel with XIP but does not set BUILTIN_DTB_SOURCE or unselect BUILTIN_DTB will not boot. Also, this patch removes the default dtb string for k210 from Kconfig to nommu_k210_defconfig and nommu_k210_sdcard_defconfig to avoid complex Kconfig settings for other SoCs in the future. [1] https://lore.kernel.org/linux-riscv/20201208073355.40828-5-damien.lemoal@wdc.com/ [2] https://lore.kernel.org/linux-riscv/20210604120639.1447869-1-alex@ghiti.fr/ [3] https://lore.kernel.org/linux-riscv/CAK7LNATt_56mO2Le4v4EnPnAfd3gC8S_Sm5-GCsfa=qXy=8Lrg@mail.gmail.com/ Signed-off-by: Yangyu Chen <cyy@cyyself.name> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-05riscv: dts: starfive: jh7100: fix root clock namesKrzysztof Kozlowski1-0/+4
JH7100 clock controller driver depends on certain root clock names. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Closes: https://lore.kernel.org/all/CAMuHMdWw0dteXO2jw4cwGvzKcL6vmnb96C=qgPgUqNDMtF6X0Q@mail.gmail.com/ Fixes: f03606470886 ("riscv: dts: starfive: replace underscores in node names") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-04Merge tag 'riscv-sophgo-dt-for-v6.9' of https://github.com/sophgo/linux into ↵Arnd Bergmann1-0/+9
soc/dt RISC-V Devicetrees for v6.9 Sophgo: Added reset support for SG2042. Also updated maintainer information for SOPHGO vendor support. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'riscv-sophgo-dt-for-v6.9' of https://github.com/sophgo/linux: MAINTAINERS: Setup proper info for SOPHGO vendor support riscv: dts: add resets property for uart node riscv: dts: add reset generator for Sophgo SG2042 SoC Link: https://lore.kernel.org/r/MA0P287MB2822315119DA51FF95EE3071FE5D2@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-03-01riscv: dts: starfive: jh7110: Add camera subsystem nodesChanghuang Liang2-0/+116
Add camera subsystem nodes for the StarFive JH7110 SoC. They contain the dphy-rx, csi2rx, camss nodes. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-02-23Merge tag 'riscv-dt-fixes-for-v6.8-rc6' of ↵Arnd Bergmann3-8/+9
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes RISC-V Devicetree fixes for v6.8-rc6 Two fixes for W=2 issues in devicetrees, which should constitute fixes for all reasonable-to-fix W=2 problems on RISC-V. The others are caused by standard USB and MMC property names containing underscores that are not likely to ever change. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-fixes-for-v6.8-rc6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: sifive: add missing #interrupt-cells to pmic riscv: dts: starfive: replace underscores in node names Link: https://lore.kernel.org/r/20240221-foil-glade-09dbf1aa3fe2@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-02-23riscv: dts: add resets property for uart nodeChen Wang1-0/+1
Add resets property for uart0 for completeness, although it is deasserted by default. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Inochi Amaoto <inochiama@outlook.com> Link: https://lore.kernel.org/r/807f75e433a0f900da40ebb6a448349c98580072.1706577450.git.unicorn_wang@outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-02-23riscv: dts: add reset generator for Sophgo SG2042 SoCChen Wang1-0/+8
Add reset generator node to device tree for SG2042. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Inochi Amaoto <inochiama@outlook.com> Link: https://lore.kernel.org/r/b2f5d7cd2d3fccfc00cf4563d2dd7363b0fa2fca.1706577450.git.unicorn_wang@outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-02-14riscv: dts: sifive: add missing #interrupt-cells to pmicConor Dooley1-0/+1
At W=2 dtc complains: hifive-unmatched-a00.dts:120.10-238.4: Warning (interrupt_provider): /soc/i2c@10030000/pmic@58: Missing '#interrupt-cells' in interrupt provider Add the missing property. Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-02-13riscv: dts: starfive: replace underscores in node namesKrzysztof Kozlowski2-8/+8
Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-02-06riscv: dts: microchip: add specific compatible for mpfs pdmaShravan Chippa1-1/+1
Add specific compatible for PolarFire SoC for The SiFive PDMA driver Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-02-06riscv: dts: microchip: add missing CAN bus clocksConor Dooley1-2/+2
The CAN controller on PolarFire SoC has an AHB peripheral clock _and_ a CAN bus clock. The bus clock was omitted when the binding was written, but is required for operation. Make up for lost time and add to the DT. Fixes: 38a71fc04895 ("riscv: dts: microchip: add mpfs's CAN controllers") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-31pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28Lad Prabhakar1-0/+4
Add the missing port pins P19 to P28 for RZ/Five SoC. These additional pins provide expanded capabilities and are exclusive to the RZ/Five SoC. Couple of port pins have different configuration and are not identical for the complete port so introduce struct rzg2l_variable_pin_cfg to handle such cases and introduce the PIN_CFG_VARIABLE macro. The actual pin config is then assigned in rzg2l_pinctrl_get_variable_pin_cfg(). Add an additional check in rzg2l_gpio_get_gpioint() to only allow GPIO pins which support interrupt facility. While at define RZG2L_GPIO_PORT_PACK() using RZG2L_GPIO_PORT_SPARSE_PACK(). Update the gpio-ranges property in the RZ/Five SoC DTSI, as it must match the driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240129135556.63466-4-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/r/20240129135556.63466-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-31riscv: dts: starfive: beaglev-starlight: Setup phy reset gpioCristian Ciocaltea1-0/+11
The BeagleV Starlight SBC uses a Microchip KSZ9031RNXCA PHY supporting RGMII-ID which doesn't require any particular setup, other than defining a reset gpio, as opposed to VisionFive V1 for which the RX internal delay had to be adjusted. Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-31riscv: dts: starfive: visionfive-v1: Setup ethernet phyCristian Ciocaltea1-1/+21
The StarFive VisionFive V1 SBC uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires manual adjustment of the RX internal delay to work properly. The default RX delay provided by the driver is 1.95 ns, which proves to be too high. Applying a 50% reduction seems to mitigate the issue. Also note this adjustment is not necessary on BeagleV Starlight SBC, which uses a Microchip PHY. Hence, there is no indication of a misbehaviour on the GMAC side, but most likely the issue stems from the Motorcomm PHY. While at it, drop the redundant gpio include, which is already provided by jh7100-common.dtsi. Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-31riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmacCristian Ciocaltea1-0/+84
Add pinmux configuration for DWMAC found on the JH7100 based boards and enable the related DT node, providing a basic PHY configuration. Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-31riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodesCristian Ciocaltea1-0/+36
Provide the sysmain and gmac DT nodes supporting the DWMAC found on the StarFive JH7100 SoC. Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-20 08:53:53 +0300