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2023-01-26riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1}Lad Prabhakar1-0/+10
IRQC support for RZ/Five is still missing so drop the interrupts and interrupt-parent properties from the PHY nodes of ETH{0,1}. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230102222708.274369-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-25Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM"Conor Dooley3-0/+184
As it says on the tin, add a DT for this board. It's been sitting on my desk for a while, so may as well have it upstream... The DT is only partially complete, as it needs the fabric content added. Unfortunately, I don't have a reference design in RTL or SmartDesign for it and therefore don't know what that fabric content is. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-01-25riscv: dts: microchip: add the Aldec TySoM's devicetreeConor Dooley3-0/+184
The TySOM-M-MPFS250 is a compact SoC prototyping board featuring a Microchip PolarFire SoC MPFS250T-FCG1152. Features include: - 16 Gib FPGA DDR4 - 16 Gib MSS DDR4 with ECC - eMMC - SPI flash memory - 2x Ethernet 10/100/1000 - USB 2.0 - PCIe x4 Gen2 - HDMI OUT - 2x FMC connector (HPC and LPC) Specifically flag this board as rev2, in case later boards have an FPGA design revision with more features available in the future. Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250 [Fixed a mistake where I read 16 Gib as 16 GiB!] Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-01-12riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodesLad Prabhakar1-8/+0
Enable OSTM{1,2} nodes on RZ/Five SMARC SoM. Note, OSTM{1,2} nodes are enabled in the RZ/G2UL SMARC SoM DTSI [0] hence deleting the disabled nodes from RZ/Five SMARC SoM DTSI enables it here too as we include [0] in RZ/Five SMARC SoM DTSI. [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230102222233.274021-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-07riscv: dts: sifive: fu740: fix size of pcie 32bit memoryBen Dooks1-1/+1
The 32-bit memory resource is needed for non-prefetchable memory allocations on the PCIe bus, however with some cards (such as the SM768) the system fails to allocate memory from this. Checking the allocation against the datasheet, it looks like there has been a mis-calcualation of the resource for the first memory region (0x0060090000..0x0070ffffff) which in the data-sheet for the fu740 (v1p2) is from 0x0060000000..0x007fffffff. Changing this to allocate from 0x0060090000..0x007fffffff fixes the probing issues. Fixes: ae80d5148085 ("riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC") Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Cc: stable@vger.kernel.org Tested-by: Ron Economos <re@w6rz.net> # from IRC Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-12-27RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOOConor Dooley5-15/+15
Convert all non user visible use of SOC_FOO symbols to their ARCH_FOO variants. The canaan DTs are an outlier in that they're gated at the directory and the file level. Drop the directory level gating while we are swapping the symbol names over. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-12-26riscv: dts: renesas: rzfive-smarc-som: Enable WDTLad Prabhakar1-4/+0
Enable WDT node on RZ/Five SMARC SoM. Note, WDT block is enabled in RZ/G2UL SMARC SoM DTSI [0] hence deleting the disabled node from RZ/Five SMARC SoM DTSI enables it here too as we include [0] in RZ/Five SMARC SoM DTSI. [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221118135715.14410-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-12-12Merge tag 'soc-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds16-203/+471
Pull ARM SoC DT updates from Arnd Bergmann: "The devicetree changes contain exactly 1000 non-merge changesets, including a number of new arm64 SoC variants from Qualcomm and Apple, as well as the Renesas r9a07g043f/u chip in both arm64 and riscv variants. While we have occasionally merged support for non-arm SoCs in the past, this is now the normal path for riscv devicetree files. The most notable changes, by SoC platform, are: - The Apple T6000 (M1 Pro), T6001 (M1 Max) and T6002 (M1 Ultra) chips now have initial support. This is particularly nice as I am typing this on a T6002 Mac Studio with only a small number of driver patches. - Qualcomm MSM8996 Pro (Snapdragon 821), SM6115 (Snapdragon 662), SM4250 (Snapdragon 460), SM6375 (Snapdragon 695), SDM670 (Snapdragon 670), MSM8976 (Snapdragon 652) and MSM8956 (Snapdragon 650) are all mobile phone chips that are closely related to others we already support. Adding those helps support more phones and we add several models from Sony (Xperia 10 IV, 5 IV, X, and X compact), OnePlus (One, 3, 3T, and Nord N100), Xiaomi (Poco F1, Mi6), Huawei (Watch) and Google (Pixel 3a). There are also new variants of the Herobrine and Trogdor chromebook motherboards. SA8540P is an automotive SoC used in the Qdrive-3 development platform - Rockchips gains no new SoC variants, but a lot of new boards: three mobile gaming systems based on RK3326 Odroid-Go/rg351 family, two more Anbernic gaming systems based on RK3566 and a number of other RK356x based single-board computers. - Renesas RZ/G2UL (r9a07g043) was already supported for arm64, but as the newly added RZ/Five is based on the same design, this now gets reorganized in order to share most of the dts description between the two and add the RZ/Five SMARC EVK board support. Aside from that, there are the usual changes all over the tree: - New boards on other platforms contain two ASpeed BMC users, two Broadcom based Wifi routers, Zyxel NSA310S NAS, the i.MX6 based Kobo Aura2 ebook reader, two i.MX8 based development boards, two Uniphier Pro5 development boards, the STM32MP1 testbench board from DHCOR, the TI K3 based BeagleBone AI-64 board, and the Mediatek Helio X10 based Sony Xperia M5 phone. - The Starfive JH7100 source gets reorganized in order to support the VisionFive V1 board. - Minor updates and cleanups for Intel SoCFPGA, Marvell PXA168, TI, ST, NXP, Apple, Broadcom, Juno, Marvell MVEBU, at91, nuvoton, Tegra, Mediatek, Renesas, Hisilicon, Allwinner, Samsung, ux500, spear, ... The treewide cleanups now have a lot of fixes for cache nodes and other binding violoations. - Somewhat larger sets of reworks for NVIDIA Tegra, Qualcomm and Renesas platforms, adding a lot more on-chip device support - A rework of the way that DTB overlays are built" * tag 'soc-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (979 commits) arm64: dts: apple: t6002: Fix GPU power domains arm64: dts: apple: t600x-pmgr: Fix search & replace typo arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes arm64: dts: apple: Rename dart-sio* to sio-dart* arch: arm64: apple: t600x: Use standard "iommu" node name arch: arm64: apple: t8103: Use standard "iommu" node name ARM: dts: socfpga: Fix pca9548 i2c-mux node name dt-bindings: iio: adc: qcom,spmi-vadc: fix PM8350 define dt-bindings: iio: adc: qcom,spmi-vadc: extend example arm64: dts: qcom: sc8280xp: fix UFS DMA coherency arm64: dts: qcom: sc7280: Add DT for sc7280-herobrine-zombie arm64: dts: qcom: sm8250-sony-xperia-edo: fix no-mmc property for SDHCI arm64: dts: qcom: sdm845-sony-xperia-tama: fix no-mmc property for SDHCI arm64: dts: qcom: sda660-inforce-ifc6560: fix no-mmc property for SDHCI arm64: dts: qcom: sa8155p-adp: fix no-mmc property for SDHCI arm64: dts: qcom: qrb5165-rb: fix no-mmc property for SDHCI arm64: dts: qcom: sm8450: align MMC node names with dtschema arm64: dts: qcom: sc7180-trogdor: use generic node names arm64: dts: qcom: sm8450-hdk: add sound support arm64: dts: qcom: sm8450: add Soundwire and LPASS ...
2022-11-23Merge tag 'riscv-dt-for-v6.2-mw0' of ↵Arnd Bergmann10-203/+271
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V DeviceTrees for v6.2 dt-bindings: - new compatibles to support the StarFive VisionFive & thead CPU cores - a fix for the PolarFire SoC's pwm binding, merged through my tree as suggested by the PWM maintainers Microchip: - Non-urgent fix for the node address not matches the reg in a way that the checkers don't complain about - Add GPIO controlled LEDs for Icicle - Support for the "CCC" clocks in the FPGA fabric. Previously these used fixed-frequency clocks in the dt, but if which CCC is in use is known, as in the v2022.09 Icicle Kit Reference Design, the rates can be read dynamically. It's an "is known" as it *can* be set via constraints in the FPGA tooling but does not have to be. - A fix for the Icicle's pwm-cells - Removal of some unused PCI clocks StarFive: - Addition of the VisionFive DT, which has been a long time coming! Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles riscv: dts: microchip: remove unused pcie clocks riscv: dts: microchip: remove pcie node from the sev kit riscv: dts: microchip: fix the icicle's #pwm-cells dt-bindings: pwm: fix microchip corePWM's pwm-cells riscv: dts: starfive: Add StarFive VisionFive V1 device tree riscv: dts: starfive: Add common DT for JH7100 based boards dt-bindings: riscv: starfive: Add StarFive VisionFive V1 board riscv: dts: microchip: fix memory node unit address for icicle riscv: dts: microchip: icicle: Add GPIO controlled LEDs riscv: dts: microchip: add the mpfs' fabric clock control Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-17riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2CLad Prabhakar1-27/+0
Enable CANFD and I2C on RZ/Five SMARC EVK. Note, these blocks are enabled in RZ/G2UL SMARC EVK DTSI [0] hence deleting these disabled nodes from RZ/Five SMARC EVK DTSI enables them here too as we include [0] in RZ/Five SMARC EVK DTSI. [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221115105135.1180490-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-17riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal ↵Lad Prabhakar2-11/+2
Zones/TSU Enable support for below blocks found on RZ/Five SMARC EVK SoC/SoM: - ADC - OPP - Thermal Zones - TSU Note, these blocks are enabled in RZ/G2UL SMARC SoM DTSI [0] hence deleting these disabled nodes from RZ/Five SMARC SoM DTSI enables them here too as we include [0] in RZ/Five SMARC SoM DTSI. [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221115105135.1180490-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-17riscv: dts: microchip: remove unused pcie clocksConor Dooley2-4/+4
The PCIe root port in the designs that ship with the PolarBerry and M100PFSEVP are connected via one, not two Fabric Interface Controllers (FIC). The one at 0x20_0000_0000 is fic0, so remove the fic1 clocks from the dt node. The same clock provides both, so this is harmless but inaccurate. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-17riscv: dts: microchip: remove pcie node from the sev kitConor Dooley1-29/+0
The SEV kit reference design does not hook up the PCIe root port to the core complex including it is misleading. The entry is a re-use mistake - I was not aware of this when I moved the PCIe node out of mpfs.dtsi so that individual bistreams could connect it to different fics etc. The node is disabled, so there should be no functional change here. Fixes: 978a17d1a688 ("riscv: dts: microchip: add sevkit device tree") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-15Merge branch 'riscv-visionfive_v1' into riscv-dt-for-nextConor Dooley4-153/+183
The VisionFive DT somehow never actually made it upstream, and is largely shared with the BeagleV. Better late than never. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-15riscv: dts: microchip: fix the icicle's #pwm-cellsConor Dooley1-1/+1
\#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 & blindly overridden by the (out of tree) driver anyway. The core can support inverted operation, so update the entry to correctly report its capabilities. Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to icicle kit") Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-10riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVKLad Prabhakar5-0/+179
Enable the minimal blocks required for booting the Renesas RZ/Five SMARC EVK with initramfs. Below are the blocks which are enabled: - CPG - CPU0 - DDR (memory regions) - PINCTRL - PLIC - SCIF0 As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and carrier [2] board DTSIs which enables almost all the blocks supported by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually enabling the blocks hence the aliases for ETH/I2C are deleted and rest of the IP blocks are marked as disabled/deleted. [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi [2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20221028165921.94487-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-10riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoCLad Prabhakar1-0/+57
Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP Single). RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. r9a07g043f.dtsi includes RZ/Five SoC specific blocks. Below are the RZ/Five SoC specific blocks added in the initial DTSI which can be used to boot via initramfs on RZ/Five SMARC EVK: - AX45MP CPU - PLIC [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20221028165921.94487-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-04riscv: dts: starfive: Add StarFive VisionFive V1 device treeCristian Ciocaltea2-1/+21
Add initial device tree for the StarFive VisionFive V1 SBC, which is similar with the already supported BeagleV Starlight Beta board, both being based on the StarFive JH7100 SoC. Link: https://github.com/starfive-tech/VisionFive Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-04riscv: dts: starfive: Add common DT for JH7100 based boardsCristian Ciocaltea2-152/+162
In preparation for adding initial device tree support for the StarFive VisionFive board, which is similar with BeagleV Starlight, move most of the content from jh7100-beaglev-starlight.dts to a new file, to be shared between the two boards. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-10-31riscv: dts: microchip: fix memory node unit address for icicleConor Dooley1-1/+1
Evidently I forgot to update the unit address for the 38-bit cached memory node when I changed the address in the reg property.. Update it to match. Fixes: 6c1193301791 ("riscv: dts: microchip: update memory configuration for v2022.10") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-10-29riscv: dts: sifive unleashed: Add PWM controlled LEDsEmil Renner Berthing1-0/+38
This adds the 4 PWM controlled green LEDs to the HiFive Unleashed device tree. The schematic doesn't specify any special function for the LEDs, so they're added here without any default triggers and named d1, d2, d3 and d4 just like in the schematic. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221012110928.352910-1-emil.renner.berthing@canonical.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-10-22riscv: dts: microchip: icicle: Add GPIO controlled LEDsEmil Renner Berthing1-0/+30
Add the 4 GPIO controlled LEDs to the Microchip PolarFire-SoC Icicle Kit device tree. The schematic doesn't specify any special function for the LEDs, so they're added here without any default triggers and named led1, led2, led3 and led4 just like in the schematic. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-10-19riscv: dts: microchip: add the mpfs' fabric clock controlConor Dooley3-15/+52
The "fabric clocks" in current PolarFire SoC device trees are not really fixed clocks. Their frequency is set by the bitstream, so having them located in -fabric.dtsi is not a problem - they're just as "fixed" as the IP blocks etc used in the FPGA fabric. However, their configuration can be read at runtime (and to an extent they can be controlled, although the intended usage is static configurations set by the bitstream) through the system controller bus. In the v2022.09 icicle kit reference design a single CCC (north-west corner) is enabled, using a 50 MHz off-chip oscillator as its reference. Updating to the v2022.09 icicle kit reference design is required, as prior to this release, the CCC was not fixed & could change for any given run of the synthesis tool. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-10-14Merge tag 'riscv-for-linus-6.1-mw2' of ↵Linus Torvalds9-39/+498
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: - DT updates for the PolarFire SOC - a fix to correct the handling of write-only mappings - m{vetndor,arcd,imp}id is now in /proc/cpuinfo - the SiFive L2 cache controller support has been refactored to also support L3 caches - misc fixes, cleanups and improvements throughout the tree * tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits) MAINTAINERS: add RISC-V's patchwork RISC-V: Make port I/O string accessors actually work riscv: enable software resend of irqs RISC-V: Re-enable counter access from userspace riscv: vdso: fix NULL deference in vdso_join_timens() when vfork riscv: Add cache information in AUX vector soc: sifive: ccache: define the macro for the register shifts soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes soc: sifive: ccache: reduce printing on init soc: sifive: ccache: determine the cache level from dts soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache riscv: check for kernel config option in t-head memory types errata riscv: use BIT() marco for cpufeature probing riscv: use BIT() macros in t-head errata init riscv: drop some idefs from CMO initialization riscv: cleanup svpbmt cpufeature probing riscv: Pass -mno-relax only on lld < 15.0.0 RISC-V: Avoid dereferening NULL regs in die() dt-bindings: riscv: add new riscv,isa strings for emulators ...
2022-10-13Merge tag 'dt-for-palmer-v6.1-mw1' of ↵Palmer Dabbelt9-39/+498
git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into for-next Microchip RISC-V devicetrees for v6.1 Fixups, reference design changes and new boards: - The addition of QSPI support for mpfs had a corresponding change to the devicetree node. - The v2022.{09,10} reference designs brought with them several memory map changes which are not backwards compatible. The old devicetrees from the v2022.08 and earlier releases still work with current kernels. - Two new devicetrees for a first-party development kit and for the Aries Embedded M100FPSEVP kit. - Corresponding dt-bindings changes for the above. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'dt-for-palmer-v6.1-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: microchip: fix fabric i2c reg size riscv: dts: microchip: update memory configuration for v2022.10 riscv: dts: microchip: add a devicetree for aries' m100pfsevp riscv: dts: microchip: add sevkit device tree riscv: dts: microchip: reduce the fic3 clock rate riscv: dts: microchip: icicle: re-jig fabric peripheral addresses riscv: dts: microchip: icicle: update pci address properties riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi riscv: dts: microchip: add pci dma ranges for the icicle kit dt-bindings: riscv: microchip: document the sev kit dt-bindings: riscv: microchip: document the aries m100pfsevp dt-bindings: riscv: microchip: document icicle reference design riscv: dts: microchip: add qspi compatible fallback Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-10-11Merge tag 'pinctrl-v6.1-1' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "There is nothing exciting going on, no core changes, just a few drivers and cleanups. New drivers: - Cypress CY8C95x0 chip pin control support, along with an immediate cleanup - Mediatek MT8188 SoC pin control support - Qualcomm SM8450 and SC8280XP LPASS (low power audio subsystem) pin control support - Qualcomm PM7250, PM8450 - Rockchip RV1126 SoC pin control support Improvements: - Fix some missing pins in the Armada 37xx driver - Convert Broadcom and Nomadik drivers to use PINCTRL_PINGROUP() macro - Fix some GPIO irq_chips to be immutable - Massive Qualcomm device tree binding cleanup, with more to come" * tag 'pinctrl-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (119 commits) MAINTAINERS: adjust STARFIVE JH7100 PINCTRL DRIVER after file movement pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100" pinctrl: Create subdirectory for StarFive drivers dt-bindings: pinctrl: st,stm32: Document interrupt-controller property dt-bindings: pinctrl: st,stm32: Document gpio-hog pattern property dt-bindings: pinctrl: st,stm32: Document gpio-line-names pinctrl: st: stop abusing of_get_named_gpio() pinctrl: wpcm450: Correct the fwnode_irq_get() return value check pinctrl: bcm: Remove unused struct bcm6328_pingroup pinctrl: qcom: restrict drivers per ARM/ARM64 pinctrl: bcm: ns: Remove redundant dev_err call gpio: rockchip: request GPIO mux to pinctrl when setting direction pinctrl: rockchip: add pinmux_ops.gpio_set_direction callback pinctrl: cy8c95x0: Align function names in cy8c95x0_pmxops pinctrl: cy8c95x0: Drop atomicity on operations on push_pull pinctrl: cy8c95x0: Lock register accesses in cy8c95x0_set_mux() pinctrl: sunxi: sun50i-h5: Switch to use dev_err_probe() helper pinctrl: stm32: Switch to use dev_err_probe() helper dt-bindings: qcom-pmic-gpio: Add PM7250B and PM8450 bindings pinctrl: qcom: spmi-gpio: Add compatible for PM7250B ...
2022-10-07riscv: dts: microchip: fix fabric i2c reg sizeConor Dooley1-1/+1
The size of the reg should've been changed when the address was changed, but obviously I forgot to do so. Fixes: ab291621a8b8 ("riscv: dts: microchip: icicle: re-jig fabric peripheral addresses") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-10-04pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"Jianlong Huang1-1/+1
Add the SoC name to make it more clear. Also the next generation StarFive SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver. No functional change. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220930061404.5418-1-hal.feng@linux.starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-09-27riscv: dts: microchip: update memory configuration for v2022.10Conor Dooley1-2/+13
In the v2022.10 reference design, the seg registers are going to be changed, resulting in a required change to the memory map in Linux. A small 4M reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use, so that it can cache its payload.bin between reboots of a specific context. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-27riscv: dts: microchip: add a devicetree for aries' m100pfsevpConor Dooley3-0/+225
Add device trees for both configs used by the Aries Embedded M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM, featuring: - 2GB DDR4 SDRAM dedicated to the HMS - 512MB DDR4 SDRAM dedicated to the FPGA - 32 MB SPI NOR Flash - 4 GByte eMMC and a carrier board with: - 2x Gigabit Ethernet - USB - 2x UART - 2x CAN - TFT connector - HSMC extension connector - 3x PMOD extension connectors - microSD-card slot Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes Link: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire-microchip-soc-fpga-m100pfsevp-riscv-hsmc-pmod Link: https://downloads.aries-embedded.de/products/M100PFS/Hardware/M100PFSEVP-Schematics.pdf Co-developed-by: Wolfgang Grandegger <wg@aries-embedded.de> Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-27riscv: dts: microchip: add sevkit device treeVattipalli Praveen3-0/+191
Add a basic dts for the Microchip Smart Embedded Vision dev kit. The SEV kit is an upcoming first party board, featuring an MPFS250T and: - Dual Sony Camera Sensors (IMX334) - IEEE 802.11 b/g/n 20MHz (1x1) Wi-Fi - Bluetooth 5 Low Energy - 4 GB DDR4 x64 - 2 GB LPDDR4 x32 - 1 GB SPI Flash - 8 GB eMMC flash & SD card slot (multiplexed) - HDMI2.0 Video Input/Output - MIPI DSI Output - MIPI CSI-2 Input Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06 Signed-off-by: Vattipalli Praveen <praveen.kumar@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-27riscv: dts: microchip: reduce the fic3 clock rateConor Dooley1-1/+1
For the v2022.09 release of the reference design, the fic3 clock rate been reduced from 62.5 MHz to 50 MHz as it allows timing to be closed significantly more quickly by customers who chose to build the reference design themselves. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-27riscv: dts: microchip: icicle: re-jig fabric peripheral addressesConor Dooley1-4/+4
When users try to add onto the reference design, they find that the current addresses that peripherals connected to Fabric InterConnect (FIC) 3 use are restrictive. For the v2022.09 reference design, the peripherals have been shifted down, leaving more contiguous address space for their custom IP/peripherals. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-27riscv: dts: microchip: icicle: update pci address propertiesConor Dooley1-5/+5
For the v2022.09 reference design the PCI root port's data region has been moved to FIC1 from FIC0. This is a shorter path, allowing for higher clock rates and improved through-put. As a result, the address at which the PCIe's data region appears to the core complex has changed. The config region's address is unchanged. As FIC0 is no longer used, its clock can be removed too. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-27riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsiConor Dooley3-33/+58
In today's edition of moving things around: The PCIe root port on PolarFire SoC is more part of the FPGA than of the Core Complex. It is located on the other side of the chip and, apart from its interrupts, most of its configuration is determined by the FPGA bitstream rather. This includes: - address translation in both directions - the addresses at which the config and data regions appear to the core complex - the clocks used by the AXI bus - the plic interrupt used Moving the PCIe node to the -fabric.dtsi makes it clearer than a singular configuration for root port is not correct & allows the base SoC dtsi to be more easily included. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-27riscv: dts: microchip: add pci dma ranges for the icicle kitConor Dooley2-2/+8
The recently removed, accidentally included, "matr0" property was used in place of a dma-ranges property. The PCI controller is non-functional with mainline Linux in the v2022.02 or later reference designs and has not worked without configuration of address-translation since v2021.08. Add the address translation that will be used by the v2022.09 reference design & update the compatible used by the dts. Since this change is not backwards compatible, update the compatible to denote this, jumping over v2022.09 directly to v2022.10. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-31riscv: dts: microchip: use an mpfs specific l2 compatibleConor Dooley1-1/+1
PolarFire SoC does not have the same l2 cache controller as the fu540, featuring an extra interrupt. Appease the devicetree checker overlords by adding a PolarFire SoC specific compatible to fix the below sort of warnings: mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts") Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-24riscv: dts: microchip: mpfs: remove pci axi address translation propertyConor Dooley1-1/+0
An AXI master address translation table property was inadvertently added to the device tree & this was not caught by dtbs_check at the time. Remove the property - it should not be in mpfs.dtsi anyway as it would be more suitable in -fabric.dtsi nor does it actually apply to the version of the reference design we are using for upstream. Link: https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide # Section 1.3.3 Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-24riscv: dts: microchip: mpfs: remove bogus card-detect-delayConor Dooley2-2/+0
Recent versions of dt-schema warn about a previously undetected undocumented property: arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: mmc@20008000: Unevaluated properties are not allowed ('card-detect-delay' was unexpected) From schema: Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml There are no GPIOs connected to MSSIO6B4 pin K3 so adding the common cd-debounce-delay-ms property makes no sense. The Cadence IP has a register that sets the card detect delay as "DP * tclk". On MPFS, this clock frequency is not configurable (it must be 200 MHz) & the FPGA comes out of reset with this register already set. Fixes: bc47b2217f24 ("riscv: dts: microchip: add the sundance polarberry") Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-24riscv: dts: microchip: mpfs: remove ti,fifo-depth propertyConor Dooley2-4/+0
Recent versions of dt-schema warn about a previously undetected undocument property on the icicle & polarberry devicetrees: arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: ethernet@20112000: ethernet-phy@8: Unevaluated properties are not allowed ('ti,fifo-depth' was unexpected) From schema: Documentation/devicetree/bindings/net/cdns,macb.yaml I know what you're thinking, the binding doesn't look to be the problem and I agree. I am not sure why a TI vendor property was ever actually added since it has no meaning... just get rid of it. Fixes: bc47b2217f24 ("riscv: dts: microchip: add the sundance polarberry") Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-24riscv: dts: microchip: mpfs: fix incorrect pcie child node nameConor Dooley1-1/+1
Recent versions of dt-schema complain about the PCIe controller's child node name: arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected) From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml Make the dts match the correct property name in the dts. Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-17riscv: dts: microchip: correct L2 cache interruptsHeinrich Schuchardt1-1/+1
The "PolarFire SoC MSS Technical Reference Manual" documents the following PLIC interrupts: 1 - L2 Cache Controller Signals when a metadata correction event occurs 2 - L2 Cache Controller Signals when an uncorrectable metadata event occurs 3 - L2 Cache Controller Signals when a data correction event occurs 4 - L2 Cache Controller Signals when an uncorrectable data event occurs This differs from the SiFive FU540 which only has three L2 cache related interrupts. The sequence in the device tree is defined by an enum: enum {         DIR_CORR = 0,         DATA_CORR,         DATA_UNCORR,         DIR_UNCORR, }; So the correct sequence of the L2 cache interrupts is interrupts = <1>, <3>, <4>, <2>; [Conor] This manifests as an unusable system if the l2-cache driver is enabled, as the wrong interrupt gets cleared & the handler prints errors to the console ad infinitum. Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") CC: stable@vger.kernel.org # 5.15: e35b07a7df9b: riscv: dts: microchip: mpfs: Group tuples in interrupt properties Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-08-15riscv: dts: microchip: add qspi compatible fallbackConor Dooley1-1/+1
The "hard" QSPI peripheral on PolarFire SoC is derived from version 2 of the FPGA IP core. The original binding had no fallback etc, so this device tree is valid as is. There was also no functional driver for the QSPI IP, so no device with a devicetree from a previous mainline release will regress. Link: https://lore.kernel.org/linux-spi/7c9f0d96-2882-964a-cd1f-916ddb3f0410@linaro.org/ Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-08-11riscv: dts: starfive: correct number of external interruptsMark Kettenis1-1/+1
The PLIC integrated on the Vic_U7_Core integrated on the StarFive JH7100 SoC actually supports 133 external interrupts. 127 of these are exposed to the outside world; the remainder are used by other devices that are part of the core-complex such as the L2 cache controller. But all 133 interrupts are external interrupts as far as the PLIC is concerned. Fix the property so that the driver can manage these additional interrupts, which is important since the interrupts for the L2 cache controller are enabled by default. Fixes: ec85362fb121 ("RISC-V: Add initial StarFive JH7100 device tree") Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220707185529.19509-1-kettenis@openbsd.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-08-11riscv: dts: sifive unmatched: Add PWM controlled LEDsEmil Renner Berthing1-0/+42
This adds the two PWM controlled LEDs to the HiFive Unmatched device tree. D12 is just a regular green diode, but D2 is an RGB diode with 3 PWM inputs controlling the three different colours. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Pavel Machek <pavel@ucw.cz> Tested-by: Ron Economos <re@w6rz.net> Link: https://lore.kernel.org/r/20220705210143.315151-5-emil.renner.berthing@canonical.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-08-11RISC-V: Canaan devicetree fixesPalmer Dabbelt7-31/+66
This series should rid us of dtbs_check errors for the RISC-V Canaan k210 based boards. To make keeping it that way a little easier, I changed the Canaan devicetree Makefile so that it would build all of the devicetrees in the directory if SOC_CANAAN. Link: https://lore.kernel.org/all/mhng-85044754-c361-40bc-a6a2-7082f35930bb@palmer-ri-x1c9/ * remotes/palmer/riscv-canaan_dt_schema: riscv: dts: canaan: build all devicetress if SOC_CANAAN riscv: dts: canaan: add specific compatible for kd233's LCD riscv: dts: canaan: fix bus {ranges,reg} warnings riscv: dts: canaan: remove spi-max-frequency from controllers riscv: dts: canaan: use custom compatible for k210 i2s riscv: dts: canaan: fix kd233 display spi frequency riscv: dts: canaan: fix mmc node names riscv: dts: canaan: fix the k210's timer nodes riscv: dts: canaan: fix the k210's memory node dt-bindings: memory-controllers: add canaan k210 sram controller dt-bindings: display: ili9341: document canaan kd233's lcd dt-bindings: display: convert ilitek,ili9341.txt to dt-schema
2022-08-07Merge tag 'riscv-for-linus-5.20-mw0' of ↵Linus Torvalds6-6/+99
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Enabling the FPU is now a static_key - Improvements to the Svpbmt support - CPU topology bindings for a handful of systems - Support for systems with 64-bit hart IDs - Many settings have been enabled in the defconfig, including both support for the StarFive systems and many of the Docker requirements There are also a handful of cleanups and improvements, as usual. * tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (28 commits) riscv: enable Docker requirements in defconfig riscv: convert the t-head pbmt errata to use the __nops macro riscv: introduce nops and __nops macros for NOP sequences RISC-V: Add fast call path of crash_kexec() riscv: mmap with PROT_WRITE but no PROT_READ is invalid riscv/efi_stub: Add 64bit boot-hartid support on RV64 riscv: cpu: Add 64bit hartid support on RV64 riscv: smp: Add 64bit hartid support on RV64 riscv: spinwait: Fix hartid variable type riscv: cpu_ops_sbi: Add 64bit hartid support on RV64 riscv: dts: sifive: "fix" pmic watchdog node name riscv: dts: canaan: Add k210 topology information riscv: dts: sifive: Add fu740 topology information riscv: dts: sifive: Add fu540 topology information riscv: dts: starfive: Add JH7100 CPU topology RISC-V: Add CONFIG_{NON,}PORTABLE riscv: config: enable SOC_STARFIVE in defconfig riscv: dts: microchip: Add mpfs' topology information riscv: Kconfig.socs: Add comments riscv: Kconfig.erratas: Add comments ...
2022-07-29Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski5-7/+7
No conflicts. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-07-21Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-0/+4
No conflicts. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-07-15riscv: dts: canaan: build all devicetress if SOC_CANAANConor Dooley1-2/+8
Testing & checking the Canaan devicetrees is inconvenient as only the devicetree corresponding to SOC_CANAAN_K210_DTB_BUILTIN will be built. Change the Makefile so that all devicetrees are built by default if SOC_CANAAN but only the one specified by SOC_CANAAN_K210_DTB_BUILTIN gets built as an object. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220705215213.1802496-14-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-20 05:52:44 +0300