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path: root/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
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2018-12-22powerpc/fsl: Use new clockgen bindingScott Wood1-2/+2
The driver retains compatibility with old device trees, but we don't want the old nodes lying around to be copied, or used as a reference (some of the mux options are incorrect), or even just being clutter. Signed-off-by: Scott Wood <oss@buserror.net> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> [scottwood: removed sysclk node added by Andy] Signed-off-by: Scott Wood <oss@buserror.net>
2015-10-28powerpc/mpc85xx: Add FSL QorIQ DPAA FMan support to the SoC device tree(s)Igal Liberman1-1/+9
Based on prior work by Andy Fleming <afleming@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-05-23powerpc/fsl: Add fsl,portid-mapping to corenet1-cf chipsScott Wood1-0/+2
Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Diana Craciun <diana.craciun@freescale.com>
2014-03-20powerpc/mpc85xx: Update clock nodes in device treeTang Yuantian1-0/+2
The following SoCs will be affected: p2041, p3041, p4080, p5020, p5040, b4420, b4860, t4240 Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2012-11-25powerpc/dma/raidengine: add raidengine deviceXuelin Shi1-0/+6
The RaidEngine is a new Freescale hardware that used for parity computation offloading in RAID5/6. This patch adds the device node in device tree and related binding documentation. Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Signed-off-by: Naveen Burmi <naveenburmi@freescale.com> Signed-off-by: Xuelin Shi <b29237@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-09-12powerpc/e5500: Add Power ISA properties to comply with ePAPR 1.1Olivia Yin1-0/+3
power-isa-version and power-isa-* are cpu node general properties defined in ePAPR. If the power-isa-version property exists, then for each category from the Categories section of Book I of the Power ISA version indicated, the existence of a property named power-isa-[CAT], where [CAT] is the abbreviated category name with all uppercase letters converted to lowercase, indicates that the category is supported by the implementation. This patch update all the e5500 platforms. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-24powerpc/85xx: Rework P5020DS device treeKumar Gala1-0/+96
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p5020-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Removed mpic interrupt-parent from sec nodes, just use top level Signed-off-by: Kumar Gala <galak@kernel.crashing.org>