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2015-08-26MIPS: Add cases for CPU_I6400Markos Chandras2-0/+5
Add a CPU_I6400 case to various switch statements, doing the same thing as for CPU_P5600. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10635/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-01MIPS: Add R16000 detectionJoshua Kinard2-0/+6
This allows the kernel to correctly detect an R16000 MIPS CPU on systems that have those. Otherwise, such systems will detect the CPU as an R14000, due to similarities in the CPU PRId value. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Cc: Linux MIPS List <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9092/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-03-31MIPS: OProfile: Allow sharing IRQ with timerJames Hogan1-1/+4
When requesting the performance counter overflow interrupt, pass flags which are compatible with the cevt-r4k driver, in particular IRQF_SHARED so that the two handlers can share the same IRQ. This is possible since release 2 of the architecture where there are separate pending interrupt bits for the timer interrupt and the performance counter interrupt. This will be necessary since the FDC interrupt can also be arbitrarily routed to a CPU interrupt, possibly sharing with the timer, the performance counters, or both, and it isn't scalable to have all the handlers able to call other handlers that may be on the same IRQ line. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Robert Richter <rric@kernel.org> Cc: linux-mips@linux-mips.org Cc: oprofile-list@lists.sf.net Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9130/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-03-31MIPS: Remove redundant IPTI==IPPCI logicJames Hogan1-2/+1
The situation where the timer interrupt is on the same line as the performance counter interrupt is handled in per_cpu_trap_init() by setting cp0_perfcount_irq to -1, so there is no need to duplicate the logic conditional upon cp0_perfcount_irq >= 0 in perf (init_hw_perf_events()) and oprofile (mipsxx_init()). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9125/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-03-31MIPS: cevt-r4k: Use CAUSEF_TI, CAUSEF_PCI constantsJames Hogan1-1/+1
Use CAUSEF_TI and CAUSEF_PCI constants from asm/mipsregs.h rather than the magic values (1 << 30) and (1 << 26). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9124/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: oprofile: Backtrace: don't fail on leaf functionsAaro Koskinen1-2/+3
Continue the backtrace if we cannot find SP adjustment and RA save. In that case, just assume the current RA. This allows us to get samples of frequent callers of e.g. GLIBC memset(). Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8109/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: oprofile: Enable backtrace on timer-based profilingAaro Koskinen1-1/+6
Allow unsupported CPU types to use backtrace with timer-based profiling. Some CPUs (notably OCTEON) lack architecture-specific oprofile driver. In such case oprofile can fallback to timer-based mode, and arch code can still provide the backtrace functionality. So just set up the backtrace hook always. Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8108/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: Loongson-3: Add oprofile supportHuacai Chen3-0/+225
Loongson-3 has two groups of performance counters, they are 4 sub- registers of CP0's REG25. This patch add oprofile support. REG25, sel 0: Perf Control of group 0; REG25, sel 1: Perf Counter of group 0; REG25, sel 2: Perf Control of group 1; REG25, sel 3: Perf Counter of group 1. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/8328/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: Add hook to get C0 performance counter interruptAndrew Bresticker1-4/+14
The hardware perf event driver and oprofile interpret the global cp0_perfcount_irq differently: in the hardware perf event driver it is an offset from MIPS_CPU_IRQ_BASE and in oprofile it is the actual IRQ number. This still works most of the time since MIPS_CPU_IRQ_BASE is usually 0, but is clearly wrong. Since the performance counter interrupt may vary from platform to platform like the C0 timer interrupt, add the optional get_c0_perfcount_int hook which returns the IRQ number of the performance counter. The hook should return < 0 if the performance counter interrupt is shared with the timer. If the hook is not present, the CPU vector reported in C0_IntCtl (cp0_perfcount_irq) is used. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7805/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: oprofile: Fix backtrace on 64-bit kernelAaro Koskinen1-1/+1
Fix incorrect cast that always results in wrong address for the new frame on 64-bit kernels. Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: stable@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8110/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-27MIPS: Add support for the M5150 processorLeonid Yegoshin2-0/+5
The M5150 core is a 32-bit MIPS RISC which implements the MIPS Architecture Release-5 in a 5-stage pipeline. In addition, it includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6596/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-27MIPS: OProfile: Add CPU_P5600 casesJames Hogan2-0/+5
Add a CPU_P5600 cpu type case in oprofile_arch_init() to use the MIPS model, and in mipsxx_init() to set the cpu_type string to "mips/P5600". Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Robert Richter <rric@kernel.org> Cc: oprofile-list@lists.sf.net Patchwork: https://patchwork.linux-mips.org/patch/6410/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-07MIPS: Add 1074K CPU support explicitly.Steven J. Hill2-0/+2
The 1074K is a multiprocessing coherent processing system (CPS) based on modified 74K cores. This patch makes the 1074K an actual unique CPU type, instead of a 74K derivative, which it is not. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6389/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-22MIPS: Add support for interAptiv coresLeonid Yegoshin2-0/+5
The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6163/
2014-01-22MIPS: Add support for the proAptiv coresLeonid Yegoshin2-0/+5
The proAptiv Multiprocessing System is a power efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The proAptiv Multiprocessing System combines a deep pipeline with multi-issue out of order execution for improved computational throughput. The proAptiv Multiprocessing System can contain one to six MIPS32r3 proAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6134/
2013-09-17MIPS: Optimize current_cpu_type() for better code.Ralf Baechle1-0/+1
o Move current_cpu_type() to a separate header file o #ifdefing on supported CPU types lets modern GCC know that certain code in callers may be discarded ideally turning current_cpu_type() into a function returning a constant. o Use current_cpu_type() rather than direct access to struct cpuinfo_mips. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5833/
2013-09-04oprofilefs_create_...() do not need superblock argumentAl Viro1-7/+7
same story as with oprofilefs_mkdir() Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-09-04oprofilefs_mkdir() doesn't need superblock argumentAl Viro1-1/+1
it's always equal to ->d_sb of the second argument (parent dentry), due to either being literally that, or ->d_sb of parent's parent. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-09-04oprofile: don't bother with passing superblock to ->create_files()Al Viro1-10/+10
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-08-05MIPS: oprofile: Fix BUG due to smp_processor_id() in preemptible code.Ralf Baechle1-1/+1
current_cpu_type() is not preemption-safe. If CONFIG_PREEMPT is enabled then mipsxx_reg_setup() can be called from preemptible state. Added get_cpu()/put_cpu() pair to make it preemption-safe. This was found while testing oprofile with CONFIG_DEBUG_PREEMPT enable. /usr/zntestsuite # opcontrol --init /usr/zntestsuite # opcontrol --setup --event=L2_CACHE_ACCESSES:500 --event=L2_CACHE_MISSES:500 --no-vmlinux /usr/zntestsuite # opcontrol --start Using 2.6+ OProfile kernel interface. BUG: using smp_processor_id() in preemptible [00000000] code: oprofiled/1362 caller is mipsxx_reg_setup+0x11c/0x164 CPU: 0 PID: 1362 Comm: oprofiled Not tainted 3.10.4 #18 Stack : 00000006 70757465 00000000 00000000 00000000 00000000 80b173f6 00000037 80b10000 00000000 80b21614 88f5a220 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 89c49c00 89c49c2c 80721254 807b7927 8012c1d0 80b10000 80721254 00000000 00000552 88f5a220 80b1335c 807b78e6 89c49ba8 ... Call Trace: [<801099a4>] show_stack+0x64/0x7c [<80665520>] dump_stack+0x20/0x2c [<803a2250>] debug_smp_processor_id+0xe0/0xf0 [<8052df24>] mipsxx_reg_setup+0x11c/0x164 [<8052cd70>] op_mips_setup+0x24/0x4c [<80529cfc>] oprofile_setup+0x5c/0x12c [<8052b9f8>] event_buffer_open+0x78/0xf8 [<801c3150>] do_dentry_open.isra.15+0x2b8/0x3b0 [<801c3270>] finish_open+0x28/0x4c [<801d49b8>] do_last.isra.41+0x2cc/0xd00 [<801d54a0>] path_openat+0xb4/0x4c4 [<801d5c44>] do_filp_open+0x3c/0xac [<801c4744>] do_sys_open+0x110/0x1f4 [<8010f47c>] stack_done+0x20/0x44 Bug reported and original patch by Jerin Jacob <jerinjacobk@gmail.com>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Jerin Jacob <jerinjacobk@gmail.com>
2013-05-08MIPS: Netlogic: Fix oprofile compile on XLR uniprocessorJayachandran C1-1/+1
The commit c783390a0ecef08df5c804f8c5f647431a04f502 [MIPS: oprofile: Support for XLR/XLS processors] causes a compilation failure when oprofile is enabled and SMP is not configured. arch/mips/oprofile/op_model_mipsxx.c: In function 'mipsxx_cpu_setup': arch/mips/oprofile/op_model_mipsxx.c:181:2: error: implicit declaration of function 'cpu_logical_map' To fix this, update oprofile_skip_cpu to not call cpu_logical_map when CONFIG_SMP is not defined. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/5037/ Acked-by: John Crispin <blogic@openwrt.org>
2013-02-21Merge branch 'mips-next-3.9' of ↵Ralf Baechle2-0/+5
git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
2013-02-17MIPS: Add support for the M14KEc core.Steven J. Hill2-0/+5
Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4682/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle3-25/+25
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-12-13Merge branch 'mips-next' of http://dev.phrozen.org/githttp/mips-next into ↵Ralf Baechle3-0/+31
mips-for-linux-next
2012-12-13MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle3-143/+0
Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-11-09MIPS: oprofile: Support for XLR/XLS processorsMadhusudan Bhat3-0/+31
Add support for XLR and XLS processors in MIPS Oprofile code. These processors are multi-threaded and have two counters per core. Each counter can track either all the events in the core (global mode), or events in just one thread. We use the counters in the global mode, and use only the first thread in each core to handle the configuration etc. Signed-off-by: Madhusudan Bhat <mbhat@netlogicmicro.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4471 Signed-off-by: John Crispin <blogic@openwrt.org>
2012-07-25Merge branches 'next/generic', 'next/alchemy', 'next/bcm63xx', ↵Ralf Baechle2-6/+5
'next/cavium', 'next/jz4740', 'next/lantiq', 'next/loongson1b' and 'next/netlogic' into mips-for-linux-next
2012-07-23MIPS: Add CPU support for Loongson1BKelvin Cheung2-0/+5
Loongson 1B is a 32-bit SoC designed by Institute of Computing Technology (ICT) and the Chinese Academy of Sciences (CAS), which implements the MIPS32 release 2 instruction set. [ralf@linux-mips.org: But which is not strictly a MIPS32 compliant device which also is why it identifies itself with the Legacy Vendor ID in the PrID register. When applying the patch I shoveled some code around to keep things in alphabetical order and avoid forward declarations.] Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: To: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: zhzhl555@gmail.com Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/3976/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-23MIPS: Remove dead code related to 1004K oprofile support.Steven J. Hill1-6/+0
Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3854/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-07MIPS: Add support for the M14Kc core.Steven J. Hill2-0/+5
[ralf@linux-mips.org: Fixed whitespace damage.] Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3773/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-26Merge branches 'fixes-for-linus', 'generic', 'cavium', 'module.h-fixes', ↵Ralf Baechle2-2/+12
'next/ath79' and 'next/lantiq' into mips-for-linux-next
2012-05-21MIPS: Remove all -Wall and almost all -Werror usage from arch/mips.Ralf Baechle1-2/+0
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-15MIPS: make oprofile use cp0_perfcount_irq if it is setFelix Fietkau1-0/+12
Make the oprofile code use the performance counters irq. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3723/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-06-15MIPS: oprofile: Add callgraph supportDaniel Kalmar4-1/+179
Stack unwinding is done by code examination. For kernelspace, the already existing unwind function is utilized that uses kallsyms to quickly find the beginning of functions. For userspace a new function was added that examines code at and before the pc. Signed-off-by: Daniel Kalmar <kalmard@homejinni.com> Signed-off-by: Gergely Kis <gergely@homejinni.com> Signed-off-by: Robert Richter <robert.richter@amd.com>
2011-03-17mips: change to new flag variablematt mooney1-1/+1
Replace EXTRA_CFLAGS with ccflags-y. Signed-off-by: matt mooney <mfm@muteddisk.com> Acked-by: WANG Cong <xiyou.wangcong@gmail.com> Signed-off-by: Michal Marek <mmarek@suse.cz>
2010-07-05MIPS: Oprofile: Fixup of loongson2_exit()Wu Zhangjin1-1/+7
When exiting from loongson2_exit(), we need to reset the counter register too, this patch adds a function reset_counters() to do it, by the way, this function will be shared by Perf. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1199/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-22MIPS: Oprofile: Loongson: Cleanup the commentsWu Zhangjin1-20/+5
Removes some out-of-date comments and empty lines. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1204/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-22MIPS: Oprofile: Loongson: Cleanup of the macrosWu Zhangjin1-11/+11
The _EXL, _KERNEL etc. bits are in the performance control register so use _PERFCTRL prefix instead of _PERFCNT. While at it make the macro more readable, use _ENABLE instead of _INT_EN suffix to describe the interrupt enable bit. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1203/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-22MIPS: Oprofile: Loongson: Remove unused variable from loongson2_cpu_setup()Wu Zhangjin1-4/+1
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1202/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-22MIPS: Oprofile: Loongson: Remove useless parenthesesWu Zhangjin1-1/+1
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1201/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-22MIPS: Oprofile: Loongson: Unify macro for setting eventsWu Zhangjin1-4/+4
Unified macro for counter0 and counter1 to set the event in the control register. This will be needed by Perf. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1200/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-16 MIPS: Oprofile: Fix Loongson irq handlerWu Zhangjin1-1/+1
The interrupt enable bit for the performance counters is in the Control Register $24, not in the counter register. loongson2_perfcount_handler(), we need to use Reported-by: Xu Hengyang <hengyang@mail.ustc.edu.cn> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1198/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2010-02-27MIPS: Loongson: Remove pointless sample_lock from oprofile code.Ralf Baechle1-7/+0
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27MIPS: Make various locks static.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27MIPS: Simplify the weak annotation with __weakWu Zhangjin1-3/+4
Found by $ find arch/mips/ -name "*.c" | xargs -i grep -H weak {} | grep -v __weak [Ralf: Made this bulletproof by including <linux/compiler.h>] Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/874/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27MIPS: Loongson: Change the Email address of Wu ZhangjinWu Zhangjin1-1/+1
Currently wuzj@lemote.com is not usable; change it to wuzhangjin@gmail.com. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: yanh@lemote.com Cc: huhb@lemote.com Cc: zhangfx@lemote.com Patchwork: http://patchwork.linux-mips.org/patch/829/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-12-17MIPS: oprofile: Only do performance counter handling for counter interruptsWu Zhangjin1-1/+4
In Loongson2f IP6 is shared by bonito and perfcounters so we need to avoid do_IRQ for perfcounter when the interrupt is from bonito. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Oprofile: Rename cpu_type from godson2 to loongson2Wu Zhangjin1-1/+1
Unify the naming method between kernel and the user-space oprofile tool. Because loongson is used instead of godson in most of the places, we agreed to use loongson instead, which will simplify future maintenance. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Acked-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-30MIPS: Loongson2: Fix typo "enalbe" -> "enable"Uwe Kleine-König1-7/+7
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Yanhua <yanh@lemote.com> Cc: Robert Richter <robert.richter@amd.com> Acked-by: Wu Zhangjin <wuzj@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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