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path: root/arch/mips/mm/tlb-r4k.c
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2012-09-14MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.Steven J. Hill1-1/+1
Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files and use new 'cpu_has_rixi' instead. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: David Daney <david.daney@cavium.com>
2012-03-28Disintegrate asm/system.h for MIPSDavid Howells1-1/+0
Disintegrate asm/system.h for MIPS. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> cc: linux-mips@linux-mips.org
2012-01-11Merge branch 'next/generic' into mips-for-linux-nextRalf Baechle1-53/+14
2012-01-11MIPS: Delete unused function add_temporary_entry.Ralf Baechle1-47/+0
Only available for R4000 style TLBs anyway and proper ordering of initialization code made this crude interface unncecessary. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-01-11MIPS: Flush huge TLBHillf Danton1-6/+14
When flushing TLB, if @vma is backed by huge page, we could flush huge TLB, due to that huge page is defined to be far from normal page. Signed-off-by: Hillf Danton <dhillf@gmail.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: "Jayachandran C." <jayachandranc@netlogicmicro.com> Patchwork: https://patchwork.linux-mips.org/patch/2825/ Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Hillf Danton <dhillf@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/3114/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-08MIPS: Fix Jazz 64-bit build error.Ralf Baechle1-0/+1
Move add_wired_entry to its own header file from where it will be always included. Patch up other users of add_wired_entry to also include the header as needed. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-10-25MIPS: Remove __init from add_wired_entry()Manuel Lauss1-2/+2
For Alchemy-PCI I need to add a wired entry after resuming from RAM; remove the __init from add_wired_entry() so that this actually works. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2684/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-04-06update David Miller's old email addressJustin P. Mattock1-1/+1
Signed-off-by: Justin P. Mattock <justinmattock@gmail.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-02-27MIPS: Implement Read Inhibit/eXecute InhibitDavid Daney1-3/+16
The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit (XI) bits in the page tables work. The upper two bits of EntryLo{0,1} are RI and XI when the feature is enabled in the PageGrain register. SmartMIPS only covers 32-bit systems. Cavium Octeon+ extends this to 64-bit systems by continuing to place the RI and XI bits in the top of EntryLo even when EntryLo is 64-bits wide. Because we need to carry the RI and XI bits in the PTE, the layout of the PTE is changed. There is a two instruction overhead in the TLB refill hot path to get the EntryLo bits into the proper position. Also the TLB load exception has to probe the TLB to check if RI or XI caused the exception. Also of note is that the layout of the PTE bits is done at compile and runtime rather than statically. In the 32-bit case this allows for the same number of PFN bits as before the patch as the _PAGE_HUGE is not supported in 32-bit kernels (we have _PAGE_NO_EXEC and _PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE). The patch is tested on Cavium Octeon+, but should also work on 32-bit systems with the Smart-MIPS ASE. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/952/ Patchwork: http://patchwork.linux-mips.org/patch/956/ Patchwork: http://patchwork.linux-mips.org/patch/962/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27MIPS: Remove #if 0 r4k_update_mmu_cache_hwbugDavid Daney1-34/+0
The function is #if 0ed out. There are no other occurrences of its name in the tree. It is safe to remove. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/936/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27MIPS: Remove probe_tlb().David Daney1-31/+0
The function probe_tlb() only does anything for processors that are not PRID_COMP_LEGACY. This is precisely the set of processors for which decode_configs() is called to do identical tlbsize probing calculations. Therefore probe_tlb() is completely redundant and may be removed. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/865/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-17MIPS: Remove useless zero initializations.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.Ralf Baechle1-0/+1
Some of the were relying into smp.h being dragged in by another header which of course is fragile. <asm/cpu-info.h> uses smp_processor_id() only in macros and including smp.h there leads to an include loop, so don't change cpu-info.h. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17MIPS: TLB support for hugetlbfs.David Daney1-11/+32
The TLB handlers need to check for huge pages and give them special handling. Huge pages consist of two contiguous sub-pages of physical memory. * Loading entrylo0 and entrylo1 need to be handled specially. * The page mask must be set for huge pages and then restored after writing the TLB entries. * The PTE for huge pages resides in the PMD, we halt traversal of the tables there. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-05-20MIPS: 64-bit: Fix system lockup.Greg Ungerer1-4/+2
The address range size calculation inside local_flush_tlb_kernel_range() is being truncated by a too small size variable holder on 64-bit systems. The truncated size can result in an erroneous tlbsize check that means we sit spinning inside a loop trying to flush a hige number of TLB entries. This is for all intents and purposes a system hang. Fix by using an appropriately sized valiable to hold the size. [Ralf: Greg's original patch submission identified the issue and fixed one instance in tlb-r4k.c but there there were several more. For consistency I also modified tlb-r3k.c even though that file is only used on 32-bit.] Signed-off-by: Greg Ungerer <gerg@snapgear.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Only write c0_framemask on CPUs which have this register.Ralf Baechle1-1/+4
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28[MIPS] All MIPS32 processors support64-bit physical addresses.Chris Dearman1-1/+1
Still, only the 4K may actually implement it. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-03-12[MIPS] Fix loads of section missmatchesRalf Baechle1-4/+4
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-03-12[MIPS] Fix typo in commentThiemo Seufer1-1/+1
We support now other page sizes as well. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-12[MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang1-1/+22
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-01-19[MIPS] Delete duplicate call to load_irq_save.Ralf Baechle1-1/+0
This call may have resulted to local_tlb_flush_range returning with interrupts disabled resulting in excessive interrupt latency. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27[MIPS] Replace BARRIER with more appropriate hazard barrier.Ralf Baechle1-13/+8
This is the unchanged part 2 of Chris' hazard cleanup. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-30Remove obsolete #include <linux/config.h>Jörn Engel1-1/+0
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-06-19[MIPS] Remove prototype for non-existing function.Ralf Baechle1-1/+0
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19[MIPS] MT: Improved multithreading support.Ralf Baechle1-17/+68
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-21[MIPS] Kill tlb-andes.c.Thiemo Seufer1-0/+5
Basically identical to c-r4k.c, so maintaining one is really enough. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix race conditions for read_c0_entryhi. Remove broken ASID masks inThiemo Seufer1-20/+29
tlb-sb1.c. Make tlb-r4k.c and tlb-sb1.c more similiar and more efficient. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Update MIPS to use the 4-level pagetable code thereby getting rid ofRalf Baechle1-1/+3
the compacrapability headers. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Formatting fixes.Maciej W. Rozycki1-9/+10
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-17Linux-2.6.12-rc2Linus Torvalds1-0/+419
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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