starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2008-04-28	[MIPS] Reimplement clear_page/copy_page	Thiemo Seufer	1	-19/+18
2008-02-01	[MIPS] Split the micro-assembler from tlbex.c.	Thiemo Seufer	1	-1/+2
2007-10-12	[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.	Ralf Baechle	1	-1/+1
2007-08-01	[MIPS] Use -Werror on subdirectories which build cleanly.	Ralf Baechle	1	-0/+2
2007-07-10	[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2	Fuxin Zhang	1	-0/+1
2007-02-27	[MIPS] Kill redundant EXTRA_AFLAGS	Atsushi Nemoto	1	-2/+0
2007-02-14	[MIPS] Unify dma-{coherent,noncoherent.ip27,ip32}	Ralf Baechle	1	-12/+2
2006-06-30	[MIPS] MIPS32/MIPS64 secondary cache management	Chris Dearman	1	-0/+1
2006-03-21	[MIPS] Kill tlb-andes.c.	Thiemo Seufer	1	-1/+1
2005-10-29	Fixup a few lose ends in explicit support for MIPS R1/R2.	Ralf Baechle	1	-2/+2
2005-10-29	Use R4000 TLB routines for SB1 also.	Ralf Baechle	1	-1/+1
2005-10-29	Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32\|64}_R1.	Ralf Baechle	1	-2/+2
2005-09-05	[PATCH] mips: clean up 32/64-bit configuration	Ralf Baechle	1	-2/+2
2005-04-17	Linux-2.6.12-rc2	Linus Torvalds	1	-0/+44