starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2015-10-02	MIPS: Fix octeon FP context switch handling	Paul Burton	1	-25/+1
2015-02-20	MIPS: OCTEON: Delete unused COP2 saving code	Aleksey Makarov	1	-26/+0
2015-02-20	MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register	Chandrakala Chavva	1	-3/+3
2015-02-20	MIPS: OCTEON: Save and restore CP2 SHA3 state	David Daney	1	-11/+32
2015-02-20	MIPS: OCTEON: Fix FP context save.	David Daney	1	-12/+7
2015-02-20	MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs	David Daney	1	-30/+98
2014-05-30	MIPS: OCTEON: Enable use of FPU	David Daney	1	-23/+61
2013-10-07	MIPS: stack protector: Fix per-task canary switch	James Hogan	1	-1/+1
2013-07-01	MIPS: r4k,octeon,r2300: stack protector: change canary per task	Gregory Fong	1	-0/+7
2013-06-13	MIPS: Move cop2 save/restore to switch_to()	Jayachandran C	1	-27/+0
2013-02-01	MIPS: Whitespace cleanup.	Ralf Baechle	1	-52/+52
2012-12-28	MIPS: Don't include <asm/page.h> unnecessarily.	Ralf Baechle	1	-1/+0
2012-07-19	MIPS: Fix race condition with FPU thread task flag during context switch.	Leonid Yegoshin	1	-1/+1
2011-04-06	update David Miller's old email address	Justin P. Mattock	1	-1/+1
2010-02-27	MIPS: Nuke trailing blank lines	Ralf Baechle	1	-1/+0
2009-09-17	MIPS: Consolidate all CONFIG_CPU_HAS_LLSC use in a single C file.	Ralf Baechle	1	-3/+0
2009-01-11	MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.	David Daney	1	-0/+506