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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
arch
/
mips
/
kernel
/
irq_cpu.c
Age
Commit message (
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)
Author
Files
Lines
2012-03-28
Disintegrate asm/system.h for MIPS
David Howells
1
-1
/
+0
2011-07-25
MIPS: Install handlers for software IRQs
Kevin Cernekee
1
-8
/
+6
2011-03-29
MIPS: Convert the irq functions to the new names
Thomas Gleixner
1
-2
/
+2
2011-03-25
MIPS: irq_cpu: Convert to new irq_chip functions
Thomas Gleixner
1
-25
/
+21
2010-10-07
MIPS: Add missing #inclusions of <linux/irq.h>
David Howells
1
-0
/
+1
2009-03-30
MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms
Ralf Baechle
1
-1
/
+2
2007-11-16
[MIPS] irq_cpu: use handle_percpu_irq handler to avoid dropping interrupts.
Ralf Baechle
1
-1
/
+1
2007-02-06
[MIPS] use name instead of typename for each irq_chip
Atsushi Nemoto
1
-2
/
+2
2007-02-06
[MIPS] Define MIPS_CPU_IRQ_BASE in generic header
Atsushi Nemoto
1
-10
/
+7
2006-12-06
[MIPS] Compile __do_IRQ() when really needed
Franck Bui-Huu
1
-10
/
+0
2006-11-30
[MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irq
Atsushi Nemoto
1
-1
/
+4
2006-11-30
[MIPS] IRQ cleanups
Atsushi Nemoto
1
-64
/
+13
2006-07-14
[MIPS] Eleminate interrupt migration helper use.
Ralf Baechle
1
-2
/
+2
2006-06-29
[PATCH] genirq: rename desc->handler to desc->chip
Ingo Molnar
1
-2
/
+2
2005-10-29
MT bulletproofing.
Ralf Baechle
1
-12
/
+67
2005-10-29
Inlining will result in back-to-back mtc0 mfc0 instructions. Break the
Ralf Baechle
1
-0
/
+2
2005-10-29
Use an irq_enable_hazard hazard barrier in unmask_mips_irq. This
Ralf Baechle
1
-0
/
+2
2005-10-29
Convert struct hw_interrupt_type initializations to ISO C99 named
Ralf Baechle
1
-8
/
+7
2005-10-29
Mask and ack CPU interrupts upon initialization. Keep the state
Maciej W. Rozycki
1
-1
/
+6
2005-04-17
Linux-2.6.12-rc2
Linus Torvalds
1
-0
/
+118