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2021-06-24KVM: stats: Separate generic stats from architecture specific onesJing Zhang1-7/+2
Generic KVM stats are those collected in architecture independent code or those supported by all architectures; put all generic statistics in a separate structure. This ensures that they are defined the same way in the statistics API which is being added, removing duplication among different architectures in the declaration of the descriptors. No functional change intended. Reviewed-by: David Matlack <dmatlack@google.com> Reviewed-by: Ricardo Koller <ricarkol@google.com> Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> Signed-off-by: Jing Zhang <jingzhangos@google.com> Message-Id: <20210618222709.1858088-2-jingzhangos@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-21MIPS: add PMD table accounting into MIPS'pmd_alloc_oneHuang Pei1-3/+7
This fixes Page Table accounting bug. MIPS is the ONLY arch just defining __HAVE_ARCH_PMD_ALLOC_ONE alone. Since commit b2b29d6d011944 (mm: account PMD tables like PTE tables), "pmd_free" in asm-generic with PMD table accounting and "pmd_alloc_one" in MIPS without PMD table accounting causes PageTable accounting number negative, which read by global_zone_page_state(), always returns 0. Signed-off-by: Huang Pei <huangpei@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-06-17KVM: switch per-VM stats to u64Paolo Bonzini1-1/+1
Make them the same type as vCPU stats. There is no reason to limit the counters to unsigned long. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-15MIPS: ralink: Define PCI_IOBASESergio Paracuellos1-0/+10
PCI_IOBASE is used to create VM maps for PCI I/O ports, it is required by generic PCI drivers to make memory mapped I/O range work. Hence define it for ralink architectures to be able to avoid parsing manually IO ranges in PCI generic driver code. Function 'plat_mem_setup' for ralink is using 'set_io_port_base' call using '0xa0000000' as address, so use the same address in the definition to align things. Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210614100617.28753-2-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-10MIPS: Do not include linux/irqdomain.h from asm/irq.hMarc Zyngier1-1/+0
Including linux/irqdomain.h from asm/irq.h is going to break as soon as linux/irqdomain.h will include linux/irq.h, so let's fix this. Code relying on linux/irqomain.h should include it directly. Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-06-08mips: ar7: convert to CONFIG_COMMON_CLKArnd Bergmann1-4/+0
Perform a minimal conversion of the ar7 clock implementation to the common clock framework. While the hardware can control the rates, this is left unchanged, and all clocks are registered as fixed-rate or fixed-divider clocks. Similarly, the clkdev lookup information is left unchanged but moved from the table format into individual allocations. There is a small increase in code size: text data bss dec hex filename 4757116 596640 91328 5445084 5315dc vmlinux-before 4806159 602360 91344 5499863 53ebd7 vmlinux-after Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-06-07pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' ↵Sergio Paracuellos1-9/+0
file Move all related code for SoC RT288X into a new driver located in 'pinctrl-rt288x.c' source file. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210604115159.8834-7-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' ↵Sergio Paracuellos1-46/+7
file Move all related code for SoC MT7620 into a new driver located in 'pinctrl-mt7620.c' source file. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210604115159.8834-6-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' ↵Sergio Paracuellos1-24/+0
file Move all related code for SoC RT305X into a new driver located in 'pinctrl-rt305x.c' source file. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210604115159.8834-5-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' ↵Sergio Paracuellos1-34/+0
file Move all related code for SoC RT3883 into a new driver located in 'pinctrl-rt3883.c' source file Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210604115159.8834-4-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: ralink: move ralink architecture pinmux header into the driverSergio Paracuellos1-52/+0
Ralink architecture is making use of the header located in 'arch/mips/include/asm/mach-ralink/pinmux.h' to stablish the mechanisms to make derived SoCs to set its pin functions and groups. In order to move all architecture pinmux into a more accurate place which is 'drivers/pinctrl/ralink' we have to first of all move this file also there with a small modification which creates 'rt2880_pinmux_init' function to allow SoCs pinctrl drivers to pass its configuration to the common code located in 'pinctrl-rt2880.c' file. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210604115159.8834-2-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-01mips: syscalls: define syscall offsets directly in <asm/unistd.h>Masahiro Yamada1-0/+4
There is no good reason to generate the syscall offset macros by scripting since they are not derived from the syscall tables. Define __NR_*_Linux macros directly in arch/mips/include/asm/unistd.h, and clean up the Makefile and the shell script. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-05-26locking/atomic: mips: move to ARCH_ATOMICMark Rutland2-37/+40
We'd like all architectures to convert to ARCH_ATOMIC, as once all architectures are converted it will be possible to make significant cleanups to the atomics headers, and this will make it much easier to generically enable atomic functionality (e.g. debug logic in the instrumented wrappers). As a step towards that, this patch migrates mips to ARCH_ATOMIC. The arch code provides arch_{atomic,atomic64,xchg,cmpxchg}*(), and common code wraps these with optional instrumentation to provide the regular functions. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Will Deacon <will@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20210525140232.53872-23-mark.rutland@arm.com
2021-05-26locking/atomic: cmpxchg: make `generic` a prefixMark Rutland1-1/+1
The asm-generic implementations of cmpxchg_local() and cmpxchg64_local() use a `_generic` suffix to distinguish themselves from arch code or wrappers used elsewhere. Subsequent patches will add ARCH_ATOMIC support to these implementations, and will distinguish more functions with a `generic` portion. To align with how ARCH_ATOMIC uses an `arch_` prefix, it would be helpful to use a `generic_` prefix rather than a `_generic` suffix. In preparation for this, this patch renames the existing functions to make `generic` a prefix rather than a suffix. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20210525140232.53872-12-mark.rutland@arm.com
2021-05-25MIPS: launch.h: add include guard to prevent build errorsRandy Dunlap1-0/+5
arch/mips/include/asm/mips-boards/launch.h needs an include guard to prevent it from being #included more than once. Prevents these build errors: In file included from ../arch/mips/mti-malta/malta-amon.c:16: ../arch/mips/include/asm/mips-boards/launch.h:8:8: error: redefinition of 'struct cpulaunch' 8 | struct cpulaunch { | ^~~~~~~~~ In file included from ../arch/mips/include/asm/mips-cps.h:13, from ../arch/mips/include/asm/smp-ops.h:16, from ../arch/mips/include/asm/smp.h:21, from ../include/linux/smp.h:114, from ../arch/mips/mti-malta/malta-amon.c:12: ../arch/mips/include/asm/mips-boards/launch.h:8:8: note: originally defined here 8 | struct cpulaunch { | ^~~~~~~~~ make[3]: [../scripts/Makefile.build:273: arch/mips/mti-malta/malta-amon.o] Error 1 (ignored) Fixes: 6decd1aad15f ("MIPS: add support for buggy MT7621S core detection") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@vger.kernel.org Cc: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> Reviewed-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-05-11hugetlb: clear huge pte during flush function on mips platformBibo Mao1-1/+7
If multiple threads are accessing the same huge page at the same time, hugetlb_cow will be called if one thread write the COW huge page. And function huge_ptep_clear_flush is called to notify other threads to clear the huge pte tlb entry. The other threads clear the huge pte tlb entry and reload it from page table, the reload huge pte entry may be old. This patch fixes this issue on mips platform, and it clears huge pte entry before notifying other threads to flush current huge page entry, it is similar with other architectures. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-05-07Merge branch 'akpm' (patches from Andrew)Linus Torvalds1-5/+0
Merge yet more updates from Andrew Morton: "This is everything else from -mm for this merge window. 90 patches. Subsystems affected by this patch series: mm (cleanups and slub), alpha, procfs, sysctl, misc, core-kernel, bitmap, lib, compat, checkpatch, epoll, isofs, nilfs2, hpfs, exit, fork, kexec, gcov, panic, delayacct, gdb, resource, selftests, async, initramfs, ipc, drivers/char, and spelling" * emailed patches from Andrew Morton <akpm@linux-foundation.org>: (90 commits) mm: fix typos in comments mm: fix typos in comments treewide: remove editor modelines and cruft ipc/sem.c: spelling fix fs: fat: fix spelling typo of values kernel/sys.c: fix typo kernel/up.c: fix typo kernel/user_namespace.c: fix typos kernel/umh.c: fix some spelling mistakes include/linux/pgtable.h: few spelling fixes mm/slab.c: fix spelling mistake "disired" -> "desired" scripts/spelling.txt: add "overflw" scripts/spelling.txt: Add "diabled" typo scripts/spelling.txt: add "overlfow" arm: print alloc free paths for address in registers mm/vmalloc: remove vwrite() mm: remove xlate_dev_kmem_ptr() drivers/char: remove /dev/kmem for good mm: fix some typos and code style problems ipc/sem.c: mundane typo fixes ...
2021-05-07mm: remove xlate_dev_kmem_ptr()David Hildenbrand1-5/+0
Since /dev/kmem has been removed, let's remove the xlate_dev_kmem_ptr() leftovers. Link: https://lkml.kernel.org/r/20210324102351.6932-3-david@redhat.com Signed-off-by: David Hildenbrand <david@redhat.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Michal Hocko <mhocko@suse.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Richard Henderson <rth@twiddle.net> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Matt Turner <mattst88@gmail.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Brian Cain <bcain@codeaurora.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: "James E.J. Bottomley" <James.Bottomley@HansenPartnership.com> Cc: Helge Deller <deller@gmx.de> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Vasily Gorbik <gor@linux.ibm.com> Cc: Christian Borntraeger <borntraeger@de.ibm.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Rich Felker <dalias@libc.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: David Hildenbrand <david@redhat.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Mikulas Patocka <mpatocka@redhat.com> Cc: Luc Van Oostenryck <luc.vanoostenryck@gmail.com> Cc: Mike Rapoport <rppt@kernel.org> Cc: Palmer Dabbelt <palmerdabbelt@google.com> Cc: Luis Chamberlain <mcgrof@kernel.org> Cc: Greentime Hu <green.hu@gmail.com> Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: "Peter Zijlstra (Intel)" <peterz@infradead.org> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Gerald Schaefer <gerald.schaefer@linux.ibm.com> Cc: Niklas Schnelle <schnelle@linux.ibm.com> Cc: Pierre Morel <pmorel@linux.ibm.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2021-05-01Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds1-13/+4
Pull kvm updates from Paolo Bonzini: "This is a large update by KVM standards, including AMD PSP (Platform Security Processor, aka "AMD Secure Technology") and ARM CoreSight (debug and trace) changes. ARM: - CoreSight: Add support for ETE and TRBE - Stage-2 isolation for the host kernel when running in protected mode - Guest SVE support when running in nVHE mode - Force W^X hypervisor mappings in nVHE mode - ITS save/restore for guests using direct injection with GICv4.1 - nVHE panics now produce readable backtraces - Guest support for PTP using the ptp_kvm driver - Performance improvements in the S2 fault handler x86: - AMD PSP driver changes - Optimizations and cleanup of nested SVM code - AMD: Support for virtual SPEC_CTRL - Optimizations of the new MMU code: fast invalidation, zap under read lock, enable/disably dirty page logging under read lock - /dev/kvm API for AMD SEV live migration (guest API coming soon) - support SEV virtual machines sharing the same encryption context - support SGX in virtual machines - add a few more statistics - improved directed yield heuristics - Lots and lots of cleanups Generic: - Rework of MMU notifier interface, simplifying and optimizing the architecture-specific code - a handful of "Get rid of oprofile leftovers" patches - Some selftests improvements" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (379 commits) KVM: selftests: Speed up set_memory_region_test selftests: kvm: Fix the check of return value KVM: x86: Take advantage of kvm_arch_dy_has_pending_interrupt() KVM: SVM: Skip SEV cache flush if no ASIDs have been used KVM: SVM: Remove an unnecessary prototype declaration of sev_flush_asids() KVM: SVM: Drop redundant svm_sev_enabled() helper KVM: SVM: Move SEV VMCB tracking allocation to sev.c KVM: SVM: Explicitly check max SEV ASID during sev_hardware_setup() KVM: SVM: Unconditionally invoke sev_hardware_teardown() KVM: SVM: Enable SEV/SEV-ES functionality by default (when supported) KVM: SVM: Condition sev_enabled and sev_es_enabled on CONFIG_KVM_AMD_SEV=y KVM: SVM: Append "_enabled" to module-scoped SEV/SEV-ES control variables KVM: SEV: Mask CPUID[0x8000001F].eax according to supported features KVM: SVM: Move SEV module params/variables to sev.c KVM: SVM: Disable SEV/SEV-ES if NPT is disabled KVM: SVM: Free sev_asid_bitmap during init if SEV setup fails KVM: SVM: Zero out the VMCB array used to track SEV ASID association x86/sev: Drop redundant and potentially misleading 'sev_enabled' KVM: x86: Move reverse CPUID helpers to separate header file KVM: x86: Rename GPR accessors to make mode-aware variants the defaults ...
2021-04-23mips: Do not include hi and lo in clobber list for R6Romain Naour1-5/+21
From [1] "GCC 10 (PR 91233) won't silently allow registers that are not architecturally available to be present in the clobber list anymore, resulting in build failure for mips*r6 targets in form of: ... .../sysdep.h:146:2: error: the register ‘lo’ cannot be clobbered in ‘asm’ for the current target 146 | __asm__ volatile ( \ | ^~~~~~~ This is because base R6 ISA doesn't define hi and lo registers w/o DSP extension. This patch provides the alternative clobber list for r6 targets that won't include those registers." Since kernel 5.4 and mips support for generic vDSO [2], the kernel fail to build for mips r6 cpus with gcc 10 for the same reason as glibc. [1] https://sourceware.org/git/?p=glibc.git;a=commit;h=020b2a97bb15f807c0482f0faee2184ed05bcad8 [2] '24640f233b46 ("mips: Add support for generic vDSO")' Signed-off-by: Romain Naour <romain.naour@gmail.com> Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-04-23MIPS: Avoid handcoded DIVU in `__div64_32' altogetherMaciej W. Rozycki1-6/+2
Remove the inline asm with a DIVU instruction from `__div64_32' and use plain C code for the intended DIVMOD calculation instead. GCC is smart enough to know that both the quotient and the remainder are calculated with single DIVU, so with ISAs up to R5 the same instruction is actually produced with overall similar code. For R6 compiled code will work, but separate DIVU and MODU instructions will be produced, which are also interlocked, so scalar implementations will likely not perform as well as older ISAs with their asynchronous MD unit. Likely still faster then the generic algorithm though. This removes a compilation error for R6 however where the original DIVU instruction is not supported anymore and the MDU accumulator registers have been removed and consequently GCC complains as to a constraint it cannot find a register for: In file included from ./include/linux/math.h:5, from ./include/linux/kernel.h:13, from mm/page-writeback.c:15: ./include/linux/math64.h: In function 'div_u64_rem': ./arch/mips/include/asm/div64.h:76:17: error: inconsistent operand constraints in an 'asm' 76 | __asm__("divu $0, %z1, %z2" \ | ^~~~~~~ ./include/asm-generic/div64.h:245:25: note: in expansion of macro '__div64_32' 245 | __rem = __div64_32(&(n), __base); \ | ^~~~~~~~~~ ./include/linux/math64.h:91:22: note: in expansion of macro 'do_div' 91 | *remainder = do_div(dividend, divisor); | ^~~~~~ This has passed correctness verification with test_div64 and reduced the module's average execution time down to 1.0404s from 1.0445s with R3400 @40MHz. The module's MIPS I machine code has also shrunk by 12 bytes or 3 instructions. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-04-21mips/bootinfo:correct some comments of fw_argxiaochuan mao1-1/+1
from arch/mips/kernel/head.S we know that use a0~a3 for fw_arg0~fw_arg3 there is some code from head.S: LONG_S a0, fw_arg0 # firmware arguments LONG_S a1, fw_arg1 LONG_S a2, fw_arg2 LONG_S a3, fw_arg3 Signed-off-by: xiaochuan mao <maoxiaochuan@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-04-21MIPS: Avoid DIVU in `__div64_32' is result would be zeroMaciej W. Rozycki1-2/+4
We already check the high part of the divident against zero to avoid the costly DIVU instruction in that case, needed to reduce the high part of the divident, so we may well check against the divisor instead and set the high part of the quotient to zero right away. We need to treat the high part the divident in that case though as the remainder that would be calculated by the DIVU instruction we avoided. This has passed correctness verification with test_div64 and reduced the module's average execution time down to 1.0445s and 0.2619s from 1.0668s and 0.2629s respectively for an R3400 CPU @40MHz and a 5Kc CPU @160MHz. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-04-21MIPS: Reinstate platform `__div64_32' handlerMaciej W. Rozycki1-16/+41
Our current MIPS platform `__div64_32' handler is inactive, because it is incorrectly only enabled for 64-bit configurations, for which generic `do_div' code does not call it anyway. The handler is not suitable for being called from there though as it only calculates 32 bits of the quotient under the assumption the 64-bit divident has been suitably reduced. Code for such reduction used to be there, however it has been incorrectly removed with commit c21004cd5b4c ("MIPS: Rewrite <asm/div64.h> to work with gcc 4.4.0."), which should have only updated an obsoleted constraint for an inline asm involving $hi and $lo register outputs, while possibly wiring the original MIPS variant of the `do_div' macro as `__div64_32' handler for the generic `do_div' implementation Correct the handler as follows then: - Revert most of the commit referred, however retaining the current formatting, except for the final two instructions of the inline asm sequence, which the original commit missed. Omit the original 64-bit parts though. - Rename the original `do_div' macro to `__div64_32'. Use the combined `x' constraint referring to the MD accumulator as a whole, replacing the original individual `h' and `l' constraints used for $hi and $lo registers respectively, of which `h' has been obsoleted with GCC 4.4. Update surrounding code accordingly. We have since removed support for GCC versions before 4.9, so no need for a special arrangement here; GCC has supported the `x' constraint since forever anyway, or at least going back to 1991. - Rename the `__base' local variable in `__div64_32' to `__radix' to avoid a conflict with a local variable in `do_div'. - Actually enable this code for 32-bit rather than 64-bit configurations by qualifying it with BITS_PER_LONG being 32 instead of 64. Include <asm/bitsperlong.h> for this macro rather than <linux/types.h> as we don't need anything else. - Finally include <asm-generic/div64.h> last rather than first. This has passed correctness verification with test_div64 and reduced the module's average execution time down to 1.0668s and 0.2629s from 2.1529s and 0.5647s respectively for an R3400 CPU @40MHz and a 5Kc CPU @160MHz. For a reference 64-bit `do_div' code where we have the DDIVU instruction available to do the whole calculation right away averages at 0.0660s for the latter CPU. Fixes: c21004cd5b4c ("MIPS: Rewrite <asm/div64.h> to work with gcc 4.4.0.") Reported-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Cc: stable@vger.kernel.org # v2.6.30+ Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-04-17KVM: Kill off the old hva-based MMU notifier callbacksSean Christopherson1-1/+0
Yank out the hva-based MMU notifier APIs now that all architectures that use the notifiers have moved to the gfn-based APIs. No functional change intended. Signed-off-by: Sean Christopherson <seanjc@google.com> Message-Id: <20210402005658.3024832-7-seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-04-17KVM: MIPS/MMU: Convert to the gfn-based MMU notifier callbacksSean Christopherson1-0/+1
Move MIPS to the gfn-based MMU notifier APIs, which do the hva->gfn lookup in common code, and whose code is nearly identical to MIPS' lookup. No meaningful functional change intended, though the exact order of operations is slightly different since the memslot lookups occur before calling into arch code. Signed-off-by: Sean Christopherson <seanjc@google.com> Message-Id: <20210402005658.3024832-5-seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-04-17KVM: MIPS: let generic code call prepare_flush_shadowPaolo Bonzini1-0/+3
Since all calls to kvm_flush_remote_tlbs must be preceded by kvm_mips_callbacks->prepare_flush_shadow, repurpose kvm_arch_flush_remote_tlb to invoke it. This makes it possible to use the TLB flushing mechanism provided by the generic MMU notifier code. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-04-17KVM: MIPS: rework flush_shadow_* callbacks into one that prepares the flushPaolo Bonzini1-8/+1
Both trap-and-emulate and VZ have a single implementation that covers both .flush_shadow_all and .flush_shadow_memslot, and both of them end with a call to kvm_flush_remote_tlbs. Unify the callbacks into one and extract the call to kvm_flush_remote_tlbs. The next patches will pull it further out of the the architecture-specific MMU notifier functions kvm_unmap_hva_range and kvm_set_spte_hva. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-04-17KVM: Move prototypes for MMU notifier callbacks to generic codeSean Christopherson1-5/+0
Move the prototypes for the MMU notifier callbacks out of arch code and into common code. There is no benefit to having each arch replicate the prototypes since any deviation from the invocation in common code will explode. No functional change intended. Signed-off-by: Sean Christopherson <seanjc@google.com> Message-Id: <20210326021957.1424875-9-seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-04-16MIPS: Loongson64: Add kexec/kdump supportHuacai Chen2-0/+35
Add kexec/kdump support for Loongson64 by: 1, Provide Loongson-specific kexec functions: loongson_kexec_prepare(), loongson_kexec_shutdown() and loongson_crash_shutdown(); 2, Provide Loongson-specific assembly code in kexec_smp_wait(); To start Loongson64, The boot CPU needs 3 parameters: fw_arg0: the number of arguments in cmdline (i.e., argc). fw_arg1: structure holds cmdline such as "root=/dev/sda1 console=tty" (i.e., argv). fw_arg2: environment (i.e., envp, additional boot parameters from LEFI). Non-boot CPUs do not need one parameter as the IPI mailbox base address. They query their own IPI mailbox to get PC, SP and GP in a loopi, until the boot CPU brings them up. loongson_kexec_prepare(): Setup cmdline for kexec/kdump. The kexec/kdump cmdline comes from kexec's "append" option string. This structure will be parsed in fw_init_cmdline() of arch/mips/fw/lib/cmdline.c. Both image ->control_code_page and the cmdline need to be in a safe memory region (memory allocated by the old kernel may be corrupted by the new kernel). In order to maintain compatibility for the old firmware, the low 2MB is reserverd and safe for Loongson. So let KEXEC_CTRL_CODE and KEXEC_ARGV_ ADDR be here. LEFI parameters may be corrupted at runtime, so backup it at mips_reboot_setup(), and then restore it at loongson_kexec_shutdown() /loongson_crash_shutdown(). loongson_kexec_shutdown(): Wake up all present CPUs and let them go to reboot_code_buffer. Pass the kexec parameters to kexec_args. loongson_crash_shutdown(): Pass the kdump parameters to kexec_args. The assembly part in kexec_smp_wait provide a routine as BIOS does, in order to keep secondary CPUs in a querying loop. The layout of low 2MB memory in our design: 0x80000000, the first MB, the first 64K, Exception vectors 0x80010000, the first MB, the second 64K, STR (suspend) data 0x80020000, the first MB, the third and fourth 64K, UEFI HOB 0x80040000, the first MB, the fifth 64K, RT-Thread for SMC 0x80100000, the second MB, the first 64K, KEXEC code 0x80108000, the second MB, the second 64K, KEXEC data Cc: Eric Biederman <ebiederm@xmission.com> Tested-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-04-16MIPS: pci-legacy: remove busn_resource fieldIlya Lipnitskiy1-1/+0
No drivers set the busn_resource field in the pci_controller struct. Commit 7ee214b540d9 ("MIPS: PCI: Remove unused busn_offset") almost removed it over 3 years ago. Remove it for good to free up memory and eliminate messages like: pci_bus 0000:00: root bus resource [??? 0x00000000 flags 0x0] Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-04-16MIPS: Fix strnlen_user access checkThomas Bogendoerfer1-2/+2
Commit 04324f44cb69 ("MIPS: Remove get_fs/set_fs") changed the access_ok for strnlen_user to check the whole range, which broke some callers of strndup_user(). Restore the old behaviour and just check the first byte. Fixes: 04324f44cb69 ("MIPS: Remove get_fs/set_fs") Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-04-13MIPS: Fix access_ok() for the last byte of user spacePaul Burton1-1/+3
The MIPS implementation of access_ok() incorrectly reports that access to the final byte of user memory is not OK, much as the alpha & SH versions did prior to commit 94bd8a05cd4d ("Fix 'acccess_ok()' on alpha and SH"). For example on a MIPS64 system with __UA_LIMIT == 0xffff000000000000 we incorrectly fail in the following cases: access_ok(0xffffffffffff, 0x1) = 0 access_ok(0xfffffffffffe, 0x2) = 0 Fix MIPS in the same way as alpha & SH, by subtracting one from the addr + size condition when size is non-zero. With this the access_ok() calls above return 1 indicating that the access may be valid. The cost of the improved check is pretty minimal - we gain 2410 bytes, or 0.03%, in kernel code size for a 64r6el_defconfig kernel built using GCC 8.1.0. Signed-off-by: Paul Burton <paul.burton@mips.com> Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-04-12MIPS: add support for buggy MT7621S core detectionIlya Lipnitskiy1-1/+22
Most MT7621 SoCs have 2 cores, which is detected and supported properly by CPS. Unfortunately, MT7621 SoC has a less common S variant with only one core. On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when starting SMP. CPULAUNCH registers can be used in that case to detect the absence of the second core and override the GCR_CONFIG PCORES field. Rework a long-standing OpenWrt patch to override the value of mips_cps_numcores on single-core MT7621 systems. Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core MT7621 device (Netgear R6220). Original 4.14 OpenWrt patch: Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7 Current 5.10 OpenWrt patch: Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904 Suggested-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-04-12MIPS: uaccess: Reduce number of nested macrosThomas Bogendoerfer1-86/+68
Clean up macros even further after removal get_fs/set_fs. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Reviewed-by: Christoph Hellwig <hch@lst.de>
2021-04-06MIPS: Remove get_fs/set_fsThomas Bogendoerfer3-313/+146
All get_fs/set_fs calls in MIPS code are gone, so remove implementation of it. With the clear separation of user/kernel space access we no longer need the EVA special handling, so get rid of that, too. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Reviewed-by: Christoph Hellwig <hch@lst.de>
2021-04-06MIPS: uaccess: Added __get/__put_kernel_nofaultThomas Bogendoerfer1-0/+24
Added __get/__put_kernel_nofault as preparation for removing get/set_fs. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Reviewed-by: Christoph Hellwig <hch@lst.de>
2021-04-06MIPS: Add support for CONFIG_DEBUG_VIRTUALFlorian Fainelli2-2/+21
Provide hooks to intercept bad usages of virt_to_phys() and __pa_symbol() throughout the kernel. To make this possible, we need to rename the current implement of virt_to_phys() into __virt_to_phys_nodebug() and wrap it around depending on CONFIG_DEBUG_VIRTUAL. A similar thing is needed for __pa_symbol() which is now aliased to __phys_addr_symbol() whose implementation is either the direct return of RELOC_HIDE or goes through the debug version. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-03-29MIPS: ralink: mt7621: add memory detection supportChuanhong Guo1-3/+4
mt7621 has the following memory map: 0x0-0x1c000000: lower 448m memory 0x1c000000-0x2000000: peripheral registers 0x20000000-0x2400000: higher 64m memory detect_memory_region in arch/mips/kernel/setup.c only adds the first memory region and isn't suitable for 512m memory detection because it may accidentally read the memory area for peripheral registers. This commit adds memory detection capability for mt7621: 1. Add the highmem area when 512m is detected. 2. Guard memcmp from accessing peripheral registers: This only happens when a user decided to change kernel load address to 256m or higher address. Since this is a quite unusual case, we just skip 512m testing and return 256m as memory size. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> [Minor commit message reword, make mt7621_memory_detect static] Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-03-25MIPS: Loongson64: Distinguish firmware dependencies DTB/LEFIQing Zhang1-1/+8
Add DTB boot support, only support Loongson-2K1000 processor for now, determine whether to use the built-in DTB or the DTB from the firmware by checking the range of CKSEG0 and XKPHYS. loongson_fw_interface will be used in the future. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Qing Zhang <zhangqing@loongson.cn> Tested-by: Ming Wang <wangming01@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-03-25MIPS: Loongson64: DeviceTree for Loongson-2K1000Qing Zhang1-0/+1
Add DeviceTree files for Loongson-2K1000 processor, currently only supports single-core boot. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Qing Zhang <zhangqing@loongson.cn> Tested-by: Ming Wang <wangming01@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-03-24MIPS: fix local_irq_{disable,enable} in asmmacro.hHuang Pei1-2/+1
commit ba9196d2e005 ("MIPS: Make DIEI support as a config option") use CPU_HAS_DIEI to indicate whether di/ei is implemented correctly, without this patch, "local_irq_disable" from entry.S in 3A1000 (with buggy di/ei) lose protection of commit e97c5b609880 ("MIPS: Make irqflags.h functions preempt-safe for non-mipsr2 cpus") Fixes: ba9196d2e005 ("MIPS: Make DIEI support as a config option") Signed-off-by: Huang Pei <huangpei@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-03-24mips: asm: octeon: A typo fix in the file cvmx-address.hBhaskar Chowdhury1-1/+1
s/techically/technically/ Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-03-12MIPS: Loongson64: Move loongson_system_configuration to loongson.hQing Zhang2-18/+18
The purpose of separating loongson_system_configuration from boot_param.h is to keep the other structure consistent with the firmware. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Qing Zhang <zhangqing@loongson.cn> Acked-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-03-12MIPS: Loongson64: Remove unused sysconf membersQing Zhang1-9/+0
We don't need them anymore, They are uniform on all Loongson64 systems and have been fixed in DeviceTree.loongson3_platform_init is replaced with DTS + driver. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Qing Zhang <zhangqing@loongson.cn> Acked-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-03-10mips: syscalls: switch to generic syscalltbl.shMasahiro Yamada1-4/+3
Many architectures duplicate similar shell scripts. This commit converts mips to use scripts/syscalltbl.sh. This also unifies syscall_table_32_o32.h and syscall_table_64_o32.h into syscall_table_o32.h. The offset parameters are unneeded here; __SYSCALL(nr, entry) is defined as 'PTR entry', so the parameter 'nr' is not used in the first place. With this commit, syscall tables and generated files are straight mapped, which makes things easier to understand. syscall_n32.tbl --> syscall_table_n32.h syscall_n64.tbl --> syscall_table_n64.h syscall_o32.tbl --> syscall_table_o32.h Then, the abi parameters are also unneeded. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-03-10MIPS: Remove KVM_TE supportThomas Bogendoerfer1-238/+0
After removal of the guest part of KVM TE (trap and emulate), also remove the host part. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-03-10MIPS: Remove KVM_GUEST supportThomas Bogendoerfer3-26/+0
KVM_GUEST is broken and unmaintained, so let's remove it. Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-03-10Merge tag 'mips-fixes_5.12_1' into mips-nextThomas Bogendoerfer1-0/+3
- fixes for boot breakage because of misaligned FDTs - fix for overwritten exception handlers - enable MIPS optimized crypto for all MIPS CPUs to improve wireguard performance
2021-03-09MIPS: kernel: Reserve exception base early to prevent corruptionThomas Bogendoerfer1-0/+3
BMIPS is one of the few platforms that do change the exception base. After commit 2dcb39645441 ("memblock: do not start bottom-up allocations with kernel_end") we started seeing BMIPS boards fail to boot with the built-in FDT being corrupted. Before the cited commit, early allocations would be in the [kernel_end, RAM_END] range, but after commit they would be within [RAM_START + PAGE_SIZE, RAM_END]. The custom exception base handler that is installed by bmips_ebase_setup() done for BMIPS5000 CPUs ends-up trampling on the memory region allocated by unflatten_and_copy_device_tree() thus corrupting the FDT used by the kernel. To fix this, we need to perform an early reservation of the custom exception space. Additional we reserve the first 4k (1k for R3k) for either normal exception vector space (legacy CPUs) or special vectors like cache exceptions. Huge thanks to Serge for analysing and proposing a solution to this issue. Fixes: 2dcb39645441 ("memblock: do not start bottom-up allocations with kernel_end") Reported-by: Kamal Dasu <kdasu.kdev@gmail.com> Debugged-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by: Mike Rapoport <rppt@linux.ibm.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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