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2020-10-16Merge tag 'dma-mapping-5.10' of git://git.infradead.org/users/hch/dma-mappingLinus Torvalds2-4/+2
Pull dma-mapping updates from Christoph Hellwig: - rework the non-coherent DMA allocator - move private definitions out of <linux/dma-mapping.h> - lower CMA_ALIGNMENT (Paul Cercueil) - remove the omap1 dma address translation in favor of the common code - make dma-direct aware of multiple dma offset ranges (Jim Quinlan) - support per-node DMA CMA areas (Barry Song) - increase the default seg boundary limit (Nicolin Chen) - misc fixes (Robin Murphy, Thomas Tai, Xu Wang) - various cleanups * tag 'dma-mapping-5.10' of git://git.infradead.org/users/hch/dma-mapping: (63 commits) ARM/ixp4xx: add a missing include of dma-map-ops.h dma-direct: simplify the DMA_ATTR_NO_KERNEL_MAPPING handling dma-direct: factor out a dma_direct_alloc_from_pool helper dma-direct check for highmem pages in dma_direct_alloc_pages dma-mapping: merge <linux/dma-noncoherent.h> into <linux/dma-map-ops.h> dma-mapping: move large parts of <linux/dma-direct.h> to kernel/dma dma-mapping: move dma-debug.h to kernel/dma/ dma-mapping: remove <asm/dma-contiguous.h> dma-mapping: merge <linux/dma-contiguous.h> into <linux/dma-map-ops.h> dma-contiguous: remove dma_contiguous_set_default dma-contiguous: remove dev_set_cma_area dma-contiguous: remove dma_declare_contiguous dma-mapping: split <linux/dma-mapping.h> cma: decrease CMA_ALIGNMENT lower limit to 2 firewire-ohci: use dma_alloc_pages dma-iommu: implement ->alloc_noncoherent dma-mapping: add new {alloc,free}_noncoherent dma_map_ops methods dma-mapping: add a new dma_alloc_pages API dma-mapping: remove dma_cache_sync 53c700: convert to dma_alloc_noncoherent ...
2020-10-13Merge branch 'work.quota-compat' of ↵Linus Torvalds1-2/+0
git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs Pull compat quotactl cleanups from Al Viro: "More Christoph's compat cleanups: quotactl(2)" * 'work.quota-compat' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: quota: simplify the quotactl compat handling compat: add a compat_need_64bit_alignment_fixup() helper compat: lift compat_s64 and compat_u64 to <asm-generic/compat.h>
2020-10-13Merge branch 'work.csum_and_copy' of ↵Linus Torvalds1-51/+17
git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs Pull copy_and_csum cleanups from Al Viro: "Saner calling conventions for csum_and_copy_..._user() and friends" [ Removing 800+ lines of code and cleaning stuff up is good - Linus ] * 'work.csum_and_copy' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: ppc: propagate the calling conventions change down to csum_partial_copy_generic() amd64: switch csum_partial_copy_generic() to new calling conventions sparc64: propagate the calling convention changes down to __csum_partial_copy_...() xtensa: propagate the calling conventions change down into csum_partial_copy_generic() mips: propagate the calling convention change down into __csum_partial_copy_..._user() mips: __csum_partial_copy_kernel() has no users left mips: csum_and_copy_{to,from}_user() are never called under KERNEL_DS sparc32: propagate the calling conventions change down to __csum_partial_copy_sparc_generic() i386: propagate the calling conventions change down to csum_partial_copy_generic() sh: propage the calling conventions change down to csum_partial_copy_generic() m68k: get rid of zeroing destination on error in csum_and_copy_from_user() arm: propagate the calling convention changes down to csum_partial_copy_from_user() alpha: propagate the calling convention changes down to csum_partial_copy.c helpers saner calling conventions for csum_and_copy_..._user() csum_and_copy_..._user(): pass 0xffffffff instead of 0 as initial sum csum_partial_copy_nocheck(): drop the last argument unify generic instances of csum_partial_copy_nocheck() icmp_push_reply(): reorder adding the checksum up skb_copy_and_csum_bits(): don't bother with the last argument
2020-10-12MIPS: cpu-probe: remove MIPS_CPU_BP_GHIST option bitThomas Bogendoerfer3-5/+0
MIPS_CPU_BP_GHIST is only set two times and more or less immediately used in cpu-probe.c itself. Remove this option to make room in options word. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-10-12MIPS: replace add_memory_region with memblockThomas Bogendoerfer2-7/+1
add_memory_region was the old interface for registering memory and was already changed to used memblock internaly. Replace it by directly calling memblock functions. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-10-12MIPS: Loongson64: Clean up numa.cTiezhu Yang1-5/+1
(1) Replace nid_to_addroffset() with nid_to_addrbase() and then remove the related useless code. (2) Since end_pfn = start_pfn + node_psize, use "node_psize" instead of "end_pfn - start_pfn" to avoid the redundant calculation. (3) After commit 6fbde6b492df ("MIPS: Loongson64: Move files to the top-level directory"), CONFIG_ZONE_DMA32 is always set for Loongson64 due to MACH_LOONGSON64 selects ZONE_DMA32, so no need to use ifdef any more, just remove it. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-10-12mips: octeon: Add Ubiquiti E200 and E220 boardsMikhail Gusarov1-0/+4
These boards are used in - Ubiquiti EdgeRouter (E200), - Ubiquiti EdgeRouter Pro (E200) and - Ubiquiti Security Gateway Pro 4 (E220). Signed-off-by: Mikhail Gusarov <dottedmag@dottedmag.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-10-08MIPS: SGI-IP28: disable use of ll/sc in kernelThomas Bogendoerfer1-1/+1
SGI-IP28 systems only use broken R10k rev 2.5 CPUs, which could lock up, if ll/sc sequences are issued in certain order. Since those systems are all non-SMP, we can disable ll/sc usage in kernel. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-10-08MIPS: tx49xx: move tx4939_add_memory_regions into only userThomas Bogendoerfer1-1/+0
tx4939_add_memory_regions() is only used in txx9/rbtx4939/prom.c. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-10-06MIPS: pgtable: Remove used PAGE_USERIO defineThomas Bogendoerfer1-2/+0
There are no users of PAGE_USERIO. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-30MIPS: process: Add prototype for function arch_dup_task_structPujin Shi1-0/+1
This commit adds a prototype to fix warning at W=1: arch/mips/kernel/process.c:95:5: error: no previous prototype for 'arch_dup_task_struct' [-Werror=missing-prototypes] Signed-off-by: Pujin Shi <shipujin.t@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-28KVM: MIPS: clean up redundant kvm_run parameters in assemblyTianjia Zhang1-2/+2
In the current kvm version, 'kvm_run' has been included in the 'kvm_vcpu' structure. For historical reasons, many kvm-related function parameters retain the 'kvm_run' and 'kvm_vcpu' parameters at the same time. This patch does a unified cleanup of these remaining redundant parameters. Signed-off-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Reviewed-by: Huacai Chen <chenhc@lemote.com> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20200623131418.31473-6-tianjia.zhang@linux.alibaba.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-27MIPS: idle: Add prototype for function check_waitPujin Shi1-0/+2
This commit adds a prototype to fix warning at W=1: arch/mips/kernel/idle.c:126:13: error: no previous prototype for 'check_wait' [-Werror=missing-prototypes] Signed-off-by: Pujin Shi <shipujin.t@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-27MIPS: Ingenic: Add system type for new Ingenic SoCs.周琰杰 (Zhou Yanjie)1-0/+2
Add JZ4775, X1000E, X2000, and X2000E system type for cat /proc/cpuinfo to give out JZ4775, X1000E, X2000 and X2000E. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-26Merge tag 'mips_fixes_5.9_3' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS fixes from Thomas Bogendoerfer: - fixed FP register access on Loongsoon-3 - added missing 1074 cpu handling - fixed Loongson2ef build error * tag 'mips_fixes_5.9_3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: BCM47XX: Remove the needless check with the 1074K MIPS: Add the missing 'CPU_1074K' into __get_cpu_type() MIPS: Loongson2ef: Disable Loongson MMI instructions MIPS: Loongson-3: Fix fp register access if MSA enabled
2020-09-25Merge branch 'master' of ↵Christoph Hellwig3-5/+0
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into dma-mapping-for-next Pull in the latest 5.9 tree for the commit to revert the V4L2_FLAG_MEMORY_NON_CONSISTENT uapi addition.
2020-09-23MIPS: Add the missing 'CPU_1074K' into __get_cpu_type()Wei Li1-0/+1
Commit 442e14a2c55e ("MIPS: Add 1074K CPU support explicitly.") split 1074K from the 74K as an unique CPU type, while it missed to add the 'CPU_1074K' in __get_cpu_type(). So let's add it back. Fixes: 442e14a2c55e ("MIPS: Add 1074K CPU support explicitly.") Signed-off-by: Wei Li <liwei391@huawei.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: malta: remove mach-malta/malta-dtshim.h header fileThomas Bogendoerfer2-25/+2
To clean up mach-* directories move external declaration of malta_dt_shim() to mips-boards/malta.h and remove malta-dtshim.h. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: malta: remove unused header fileThomas Bogendoerfer1-33/+0
Remove unused heasder file asm/mach-malta/malta-pm.h. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: alchemy: remove unused ALCHEMY_GPIOINT_AU1300Thomas Bogendoerfer1-137/+0
Remove unused config option ALCHEMY_GPIOINT_AU1300 and related code. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: SGI-IP30: Move irq bits to better header filesThomas Bogendoerfer2-87/+51
Move HEART specific parts of mach-ip30/irq.h to asm/sgi/heart.h and IP30 specific parts to sgi-ip30/ip30-common.h. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: Loongson-3: Enable COP2 usage in kernelHuacai Chen2-3/+10
Loongson-3's COP2 is Multi-Media coprocessor, it is disabled in kernel mode by default. However, gslq/gssq (16-bytes load/store instructions) overrides the instruction format of lwc2/swc2. If we wan't to use gslq/ gssq for optimization in kernel, we should enable COP2 usage in kernel. Please pay attention that in this patch we only enable COP2 in kernel, which means it will lose ST0_CU2 when a process go to user space (try to use COP2 in user space will trigger an exception and then grab COP2, which is similar to FPU). And as a result, we need to modify the context switching code because the new scheduled process doesn't contain ST0_CU2 in its THERAD_STATUS probably. For zboot, we disable gslq/gssq be generated by toolchain. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21MIPS: context switch: Use save/restore instead of set/clear for Status.CU2Huacai Chen1-1/+3
Some processors (such as Loongson-3) need to enable CU2 in kernel mode, current set/clear method will lose Status.CU2 during context switching, so use save/restore method instead. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: jz4740: Rename jz4740 folders to ingenicPaul Cercueil1-0/+0
Now that all the jz4740 platform code has been removed, and we're left with only a Kconfig and the cpu-feature-overrides.h file, finalize the cleanup process by renaming the jz4740 and include/mach-jz4740 folders to ingenic and include/mach-ingenic. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: jz4740: Drop all obsolete filesPaul Cercueil1-13/+0
Support for Ingenic SoCs is now provided by the arch/mips/generic/ code, so all files in the arch/mips/jz4740/ folder can dropped, except for the Kconfig, and the cpu-feature-overrides.h header file. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: generic: Increase NR_IRQS to 256Paul Cercueil1-1/+1
128 IRQs is not enough to support Ingenic SoCs. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WAPaul Cercueil1-5/+0
Previously, in cpu_probe_ingenic(), c->writecombine was set to _CACHE_UNCACHED_ACCELERATED, but this macro was defined differently when CONFIG_MACH_INGENIC was set. This made it impossible to support multiple CPUs. Address this issue by setting c->writecombine to _CACHE_CACHABLE_WA directly and removing the dependency on CONFIG_MACH_INGENIC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: Loongson64: Increase NR_IRQS to 320Huacai Chen1-1/+2
Modernized Loongson64 uses a hierarchical organization for interrupt controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) is not enough to represent all interrupts, so let's increase NR_IRQS to 320 (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256). Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: netlogic: Remove unused codeYouling Tang1-15/+0
Remove some unused code. Signed-off-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18MIPS: Correct the header guard of r4k-timer.hWei Li1-3/+3
Rename the header guard of r4k-timer.h from __ASM_R4K_TYPES_H to __ASM_R4K_TIMER_H what corresponding with the file name. Signed-off-by: Wei Li <liwei391@huawei.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-17compat: lift compat_s64 and compat_u64 to <asm-generic/compat.h>Christoph Hellwig1-2/+0
lift the compat_s64 and compat_u64 definitions into common code using the COMPAT_FOR_U64_ALIGNMENT symbol for the x86 special case. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2020-09-11dma-direct: rename and cleanup __phys_to_dmaChristoph Hellwig1-1/+1
The __phys_to_dma vs phys_to_dma distinction isn't exactly obvious. Try to improve the situation by renaming __phys_to_dma to phys_to_dma_unencryped, and not forcing architectures that want to override phys_to_dma to actually provide __phys_to_dma. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
2020-09-11dma-direct: remove __dma_to_physChristoph Hellwig1-1/+1
There is no harm in just always clearing the SME encryption bit, while significantly simplifying the interface. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
2020-09-11MIPS/jazzdma: remove the unused vdma_remap functionChristoph Hellwig1-2/+0
Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07MIPS: Remove mach-*/war.hThomas Bogendoerfer13-132/+0
After conversion of all WAR defines we can now remove all mach-*/war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WARThomas Bogendoerfer1-3/+0
CAVIUM_OCTEON_DCACHE_PREFETCH_WAR is a check for Octeon model CN6XXXX. By using the version check we can remove the define. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07MIPS: Get rid of BCM1250_M3_WARThomas Bogendoerfer13-50/+0
BCM1250_M3_WAR is depending on CONFIG_CONFIG_SB1_PASS_2_WORKAROUNDS. So using this option directly lets and remove define. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDSThomas Bogendoerfer13-20/+0
SB1250 uart bug is related to PASS 2 workarounds. Use config CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config optionThomas Bogendoerfer14-22/+2
Use a new config option to enable MIPS 34K ITLB workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07MIPS: Convert R10000_LLSC_WAR info a config optionThomas Bogendoerfer16-29/+5
Use a new config option to enabel R1000_LLSC workaound and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config optionThomas Bogendoerfer13-22/+0
Use a new config option to enable I-cache refill workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config optionThomas Bogendoerfer13-23/+0
Use a new config option to enable TX49XX I-cache index invalidate workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WARThomas Bogendoerfer13-59/+0
Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented, so removing defines for it won't change anything. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07MIPS: Convert R4600_V2_HIT_CACHEOP into a config optionThomas Bogendoerfer13-36/+0
Use a new config option to enable R4600 V2 cacheop hit workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07MIPS: Convert R4600_V1_HIT_CACHEOP into a config optionThomas Bogendoerfer13-43/+0
Use a new config option to enable R4600 V1 cacheop hit workaround and remove define from the different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config optionThomas Bogendoerfer13-22/+0
Use a new config option to enable R4600 V1 index I-cacheop workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-04Merge tag 'mips_fixes_5.9_1' of ↵Linus Torvalds3-5/+0
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS fixes from Thomas Bogendoerfer: "A few MIPS fixes: - fallthrough fallout fix - BMIPS fixes - MSA fix to avoid leaking MSA register contents - Loongson perf and cpu feature fix - SNI interrupt fix" * tag 'mips_fixes_5.9_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: SNI: Fix SCSI interrupt MIPS: add missing MSACSR and upper MSA initialization MIPS: perf: Fix wrong check condition of Loongson event IDs mips/oprofile: Fix fallthrough placement MIPS: Loongson64: Remove unnecessary inclusion of boot_param.h MIPS: BMIPS: Also call bmips_cpu_setup() for secondary cores MIPS: mm: BMIPS5000 has inclusive physical caches MIPS: Loongson64: Do not override watch and ejtag feature
2020-08-30Merge tag 'locking-urgent-2020-08-30' of ↵Linus Torvalds1-0/+5
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull locking fixes from Thomas Gleixner: "A set of fixes for lockdep, tracing and RCU: - Prevent recursion by using raw_cpu_* operations - Fixup the interrupt state in the cpu idle code to be consistent - Push rcu_idle_enter/exit() invocations deeper into the idle path so that the lock operations are inside the RCU watching sections - Move trace_cpu_idle() into generic code so it's called before RCU goes idle. - Handle raw_local_irq* vs. local_irq* operations correctly - Move the tracepoints out from under the lockdep recursion handling which turned out to be fragile and inconsistent" * tag 'locking-urgent-2020-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: lockdep,trace: Expose tracepoints lockdep: Only trace IRQ edges mips: Implement arch_irqs_disabled() arm64: Implement arch_irqs_disabled() nds32: Implement arch_irqs_disabled() locking/lockdep: Cleanup x86/entry: Remove unused THUNKs cpuidle: Move trace_cpu_idle() into generic code cpuidle: Make CPUIDLE_FLAG_TLB_FLUSHED generic sched,idle,rcu: Push rcu_idle deeper into the idle path cpuidle: Fixup IRQ state lockdep: Use raw_cpu_*() for per-cpu variables
2020-08-26mips: Implement arch_irqs_disabled()Peter Zijlstra1-0/+5
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Paul Burton <paulburton@kernel.org> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20200826101653.GE1362448@hirez.programming.kicks-ass.net
2020-08-26MIPS: Remove unused header file m48t37.hThomas Bogendoerfer1-36/+0
No users -> remove it. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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