starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2020-09-21	MIPS: malta: remove mach-malta/malta-dtshim.h header file	Thomas Bogendoerfer	1	-25/+0
2020-09-21	MIPS: malta: remove unused header file	Thomas Bogendoerfer	1	-33/+0
2020-09-07	MIPS: Remove mach-*/war.h	Thomas Bogendoerfer	1	-11/+0
2020-09-07	MIPS: Get rid of BCM1250_M3_WAR	Thomas Bogendoerfer	1	-2/+0
2020-09-07	MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS	Thomas Bogendoerfer	1	-1/+0
2020-09-07	MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option	Thomas Bogendoerfer	1	-1/+0
2020-09-07	MIPS: Convert R10000_LLSC_WAR info a config option	Thomas Bogendoerfer	1	-1/+0
2020-09-07	MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config option	Thomas Bogendoerfer	1	-1/+0
2020-09-07	MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option	Thomas Bogendoerfer	1	-1/+0
2020-09-07	MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR	Thomas Bogendoerfer	1	-2/+0
2020-09-07	MIPS: Convert R4600_V2_HIT_CACHEOP into a config option	Thomas Bogendoerfer	1	-1/+0
2020-09-07	MIPS: Convert R4600_V1_HIT_CACHEOP into a config option	Thomas Bogendoerfer	1	-1/+0
2020-09-07	MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option	Thomas Bogendoerfer	1	-1/+0
2020-03-19	MIPS: Add header files reference with path prefix	bibo mao	1	-1/+1
2019-07-24	MIPS: Remove unused R5432_CP0_INTERRUPT_WAR	Paul Burton	1	-1/+0
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 182	Thomas Gleixner	1	-13/+1
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152	Thomas Gleixner	2	-10/+2
2017-11-03	Update MIPS email addresses	Paul Burton	2	-2/+2
2017-11-02	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	Greg Kroah-Hartman	2	-0/+2
2016-05-28	MIPS: Add definitions of SegCtl registers and use them	Matt Redfearn	1	-3/+3
2015-11-11	MIPS: Malta: Setup RAM regions via DT	Paul Burton	1	-0/+29
2014-11-24	irqchip: mips-gic: Probe for number of external interrupts	Andrew Bresticker	1	-1/+0
2014-08-19	MIPS: Malta: EVA: Rename 'eva_entry' to 'platform_eva_init'	Markos Chandras	1	-6/+16
2014-08-02	MIPS: GIC: Move GIC_NUM_INTRS into platform irq.h	Jeffrey Deans	1	-0/+1
2014-05-30	MIPS: Malta: add suspend state entry code	Paul Burton	1	-0/+37
2014-05-24	MIPS: MT: Remove SMTC support	Ralf Baechle	1	-30/+0
2014-03-27	MIPS: malta: Add support for SMP EVA	Markos Chandras	1	-0/+6
2014-03-27	MIPS: malta: spaces.h: Add spaces.h file for Malta (EVA)	Markos Chandras	1	-0/+46
2014-03-27	MIPS: malta: Configure Segment Control registers for EVA boot	Markos Chandras	1	-1/+108
2013-02-01	MIPS: Whitespace cleanup.	Ralf Baechle	3	-6/+6
2012-12-13	MIPS: PMC-Sierra Yosemite: Remove support.	Ralf Baechle	1	-1/+0
2011-07-25	MIPS: Enable cpu_has_clo_clz for MIPS Technologies' platforms	Shinya Kuribayashi	1	-0/+2
2009-09-17	MIPS: Malta: Remove pointless use use of CONFIG_CPU_HAS_LLSC	Ralf Baechle	1	-4/+0
2008-10-11	MIPS: Move headfiles to new location below arch/mips/include	Ralf Baechle	6	-0/+225