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2022-11-20ARM: dts: aspeed: bletchley: Update fusb302 nodesPotin Lai1-48/+102
1. Add interrupt pin of fusb302 on each sled. 2. Add vbus-supply property in each fusb302 node. 3. Fix BMC power-role at source and data-role at host. 4. Disable PD to avoid "HARD Reset" due to incompatible PD ver. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-5-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Bind presence-sledX pins via gpio-keysPotin Lai1-0/+35
Bind presence-sledX pins via gpio-keys driver to monitor and export GPIO pin values on DBUS using phosphor-gpio-presence service. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-4-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Disable GPIOV2 pull-downPotin Lai1-0/+10
The external pull-up cannot drive GPIOV2, so disable GPIOV2 internal pull-down resistor by the request form HW team. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-3-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Change LED sys_log_id to active lowPotin Lai1-1/+1
change LED sys_log_id to active low base on DVT schematic. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-2-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-19ARM: dts: imx6q-prti6q: Fix ref/tcxo-clock-frequency propertiesFabio Estevam1-2/+2
make dtbs_check gives the following errors: ref-clock-frequency: size (9) error for type uint32 tcxo-clock-frequency: size (9) error for type uint32 Fix it by passing the frequencies inside < > as documented in Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml. Signed-off-by: Fabio Estevam <festevam@denx.de> Fixes: 0d446a505592 ("ARM: dts: add Protonic PRTI6Q board") Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19ARM: mxs: fix memory leak in mxs_machine_init()Zheng Yongjun1-1/+3
If of_property_read_string() failed, 'soc_dev_attr' should be freed before return. Otherwise there is a memory leak. Fixes: 2046338dcbc6 ("ARM: mxs: Use soc bus infrastructure") Signed-off-by: Zheng Yongjun <zhengyongjun3@huawei.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19ARM: dts: colibri-imx6ull: Enable dual-role switchingPhilippe Schenker1-0/+29
The Colibri standard provides a GPIO called USBC_DET to switch from USB Host to USB Device and back. Make use of this GPIO by adding it with usb-connector framework. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19ARM: kexec: make machine_crash_nonpanic_core() staticChen Lifu1-1/+1
This symbol is not used outside of the file, so mark it static. Fixes the following warning: arch/arm/kernel/machine_kexec.c:76:6: warning: symbol 'machine_crash_nonpanic_core' was not declared. Should it be static? Link: https://lkml.kernel.org/r/20220929042936.22012-5-bhe@redhat.com Signed-off-by: Chen Lifu <chenlifu@huawei.com> Signed-off-by: Baoquan He <bhe@redhat.com> Acked-by: Baoquan He <bhe@redhat.com> Cc: "Eric W . Biederman" <ebiederm@xmission.com> Cc: Petr Mladek <pmladek@suse.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Jianglei Nie <niejianglei2021@163.com> Cc: Li Chen <lchen@ambarella.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Paul Mackerras <paulus@samba.org> Cc: ye xingchen <ye.xingchen@zte.com.cn> Cc: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2022-11-18arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc nodeDinh Nguyen7-0/+7
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18arm: dts: socfpga: remove "clk-phase" in sdmmc_clkDinh Nguyen2-2/+0
Now that the SDMMC driver can use the "clk-phase-sd-hs" binding, we don't need the clk-phase in the sdmmc_clk anymore. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18arm: dts: socfpga: align mmc node names with dtschemaDinh Nguyen5-5/+5
dwmmc0@ff704000: $nodename:0: 'dwmmc0@ff704000' does not match '^mmc(@.*)?$' Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18Merge tag 'wireless-next-2022-11-18' of ↵David S. Miller1-1/+0
git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next Kalle Valo says: ==================== wireless-next patches for v6.2 Second set of patches for v6.2. Only driver patches this time, nothing really special. Unused platform data support was removed from wl1251 and rtw89 got WoWLAN support. Major changes: ath11k * support configuring channel dwell time during scan rtw89 * new dynamic header firmware format support * Wake-over-WLAN support rtl8xxxu * enable IEEE80211_HW_SUPPORT_FAST_XMIT ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2022-11-18ARM: dts: lpc32xx: trim addresses to 8 digitsKrzysztof Kozlowski1-1/+1
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Link: https://lore.kernel.org/r/20221115105049.95313-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-18ARM: dts: imx: trim addresses to 8 digitsKrzysztof Kozlowski1-1/+1
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Link: https://lore.kernel.org/r/20221115105051.95345-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-18ARM: dts: omap: trim addresses to 8 digitsKrzysztof Kozlowski9-11/+11
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Reviewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20221115105053.95430-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-18stackprotector: actually use get_random_canary()Jason A. Donenfeld1-8/+1
The RNG always mixes in the Linux version extremely early in boot. It also always includes a cycle counter, not only during early boot, but each and every time it is invoked prior to being fully initialized. Together, this means that the use of additional xors inside of the various stackprotector.h files is superfluous and over-complicated. Instead, we can get exactly the same thing, but better, by just calling `get_random_canary()`. Acked-by: Guo Ren <guoren@kernel.org> # for csky Acked-by: Catalin Marinas <catalin.marinas@arm.com> # for arm64 Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
2022-11-18treewide: use get_random_u32_below() instead of deprecated functionJason A. Donenfeld1-1/+1
This is a simple mechanical transformation done by: @@ expression E; @@ - prandom_u32_max + get_random_u32_below (E) Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Darrick J. Wong <djwong@kernel.org> # for xfs Reviewed-by: SeongJae Park <sj@kernel.org> # for damon Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> # for infiniband Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> # for arm Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # for mmc Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
2022-11-18ARM: tegra: Remove duplicate pin entry in pinmuxThierry Reding1-1/+0
For Tegra30 Pegatron Chagall, the sdmmc3_dat3_pb5 pin was defined multiple times, leading to a DT validation error. Remove the duplicate entry. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Remove unused interrupt-parent propertiesThierry Reding2-4/+0
Some boards are using the interrupt-parent property to point at the GPIO controller since it handles the interrupts for the GPIO keys. However, a node needs an interrupts property for interrupt-parent to be meaningful, which these boards don't have. gpio-keys in these cases will directly use the GPIO lines specified in the key definitions and rely on the implicit conversion of those GPIOs to interrupts by the operating system, so explicit specification of the interrupts is not required. Remove the unnecessary interrupt-parent properties. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Fix nvidia,io-reset propertiesThierry Reding2-8/+8
Rename the unknown nvidia,ioreset property to nvidia,io-reset, as specified in the DT bindings and supported by the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Add missing power-supply for panelsThierry Reding3-0/+3
Tegra124 Nyan and Venice 2 boards were missing the required power-supply property in their display panel device tree nodes. Add these properties to fix validation errors. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Fixup pinmux node namesThierry Reding9-30/+30
Pinmux node names should have a pinmux- prefix and not use underscores. Fix up some cases that didn't follow those rules. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Use correct compatible string for ASUS TF101 panelThierry Reding1-1/+1
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-17ARM: at91: rm9200: fix usb device clock idMichael Grzeschik1-1/+1
Referring to the datasheet the index 2 is the MCKUDP. When enabled, it "Enables the automatic disable of the Master Clock of the USB Device Port when a suspend condition occurs". We fix the index to the real UDP id which "Enables the 48 MHz clock of the USB Device Port". Cc: nicolas.ferre@microchip.com Cc: ludovic.desroches@microchip.com Cc: alexandre.belloni@bootlin.com Cc: mturquette@baylibre.com Cc: sboyd@kernel.org Cc: claudiu.beznea@microchip.com Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: kernel@pengutronix.de Fixes: 02ff48e4d7f7 ("clk: at91: add at91rm9200 pmc driver") Fixes: 0e0e528d8260 ("ARM: dts: at91: rm9200: switch to new clock bindings") Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221114185923.1023249-2-m.grzeschik@pengutronix.de
2022-11-17ARM: dts: at91: sama7g5: fix signal name of pin PD8Mihai Sain1-1/+1
The signal name of pin PD8 with function D is A22_NANDCLE as it is defined in the datasheet. Signed-off-by: Mihai Sain <mihai.sain@microchip.com> [claudiu.beznea: rebased on top of 6.1-rc1, removed fixes tag] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221114151035.2926-1-mihai.sain@microchip.com
2022-11-17ARM: dts: at91: sam9g20ek: enable udc vbus gpio pinctrlMichael Grzeschik1-0/+9
We set the PIOC to GPIO mode. This way the pin becomes an input signal will be usable by the controller. Without this change the udc on the 9g20ek does not work. Cc: nicolas.ferre@microchip.com Cc: ludovic.desroches@microchip.com Cc: alexandre.belloni@bootlin.com Cc: linux-arm-kernel@lists.infradead.org Cc: kernel@pengutronix.de Fixes: 5cb4e73575e3 ("ARM: at91: add at91sam9g20ek boards dt support") Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221114185923.1023249-3-m.grzeschik@pengutronix.de
2022-11-17ARM: dts: stm32: Rename mdio0 to mdio on DHCOR Testbench boardMarek Vasut1-1/+1
Replace "mdio0" node with "mdio" to match mdio.yaml DT schema. Fixes: c8ce0dd75515b ("ARM: dts: stm32: Add DHCOR based Testbench board") Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-11-17ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dkAmelie Delaunay1-0/+14
MCP23017 is an IO expander offering 16 input/output port expander with interrupt output. On stm32mp135f-dk, only INTA is routed (on PG12), but MCP23017 can mirror the bank B interrupts on INTA, that's why the property microchip,irq-mirror is used. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-11-17ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13Amelie Delaunay1-0/+7
MCP23017 interrupt line (routed on PG12) requires to be pulled-up. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-11-17Merge tag 'imx-fixes-6.1-2' of ↵Arnd Bergmann1-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes i.MX fixes for 6.1, 2nd round: - Switch to usb-role-switch for fixing USB device mode on tqma8mqml-mba8mx board, so that Dual Role is fully functional. - A series from Marek Vasut to fix dt-schema warning caused by NAND controller size-cells. - Fix file permission of imx93-pinfunc header. - Enable OCOTP clock in soc-imx8m driver to fix a kexec kernel hang issue. * tag 'imx-fixes-6.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx8m: Enable OCOTP clock before reading the register arm64: dts: imx93-pinfunc: drop execution permission arm64: dts: imx8mn: Fix NAND controller size-cells arm64: dts: imx8mm: Fix NAND controller size-cells ARM: dts: imx7: Fix NAND controller size-cells arm64: dts: imx8mm-tqma8mqml-mba8mx: Fix USB DR Link: https://lore.kernel.org/r/20221116090402.GA1274@T480 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-16ARM: dts: sunxi: H3/H5: Add phys property to USB HCI0Andre Przywara1-0/+4
As many other Allwinner SoCs from the last years, the first USB host controller pair in the Allwinner H3 and H5 chips share a USB PHY with the MUSB OTG controller. This is probably the reason why we didn't have a "phys" property in those host controller nodes. This works fine as long as the MUSB controller driver is loaded, as this takes care of the proper PHY setup, including the muxing between MUSB and the HCI. However this requires the MUSB driver to be enabled and loaded, and also upsets U-Boot, which cannot use a HCI port without a "phys" property. Similar to what we did in commit cc72570747e4 ("arm64: dts: allwinner: A64: properly connect USB PHY to port 0"), add the "phys" property to the OHCI0 and EHCI0 DT nodes in the shared H3/H5 .dtsi file. This is not only the proper description of the hardware, but also avoids a nasty error message in U-Boot triggered by a recent patch. (The port never worked in host mode, but the error was suppressed due to a bug.) When using the MUSB port in OTG mode, this also fixes host mode switching, so people can use OTG adapters to connect a USB device to port 0. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221110005507.19464-1-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16ARM: dts: suniv: f1c100s: add LRADC nodeAndre Przywara1-0/+8
The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC) compatible to the version in other SoCs. The manual doesn't mention the ratio of the input voltage that is used, but comparing actual measurements with the values in the register suggests that it is 3/4 of Vref. Add the DT node describing the base address and interrupt. As in the older SoCs, there is no explicit reset or clock gate, also there is a dedicated, non-multiplexed pin, so need for more properties. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-8-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16ARM: dts: suniv: f1c100s: add CIR DT nodeAndre Przywara1-0/+11
The CIR (infrared receiver) controller in the Allwinner F1C100s series of SoCs is compatible to the ones used in other Allwinner SoCs. Add the DT node describing the resources of the controller. There are multiple possible pinmuxes, but none as them seem to be an obvious choice, so refrain from adding any pincontroller subnodes for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-7-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16ARM: dts: suniv: f1c100s: add I2C DT nodesAndre Przywara1-0/+42
The Allwinner F1C100s series of SoCs contain three I2C controllers compatible to the ones used in other Allwinner SoCs. Add the DT nodes describing the resources of the controllers. At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so include those pins already, to simplify referencing them later. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-4-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16ARM: dts: suniv: f1c100s: add PWM nodeAndre Przywara1-0/+9
The Allwinner F1C100s family of SoCs contain a PWM controller compatible to the one used in the A20 chip. Add the DT node so that any users can simply enable it in their board DT. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221107005433.11079-3-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-11-16ARM: OMAP2+: pdata-quirks: stop including wl12xx.hDmitry Torokhov1-1/+0
As of commit 2398c41d6432 ("omap: pdata-quirks: remove openpandora quirks for mmc3 and wl1251") the code no longer creates an instance of wl1251_platform_data, so there is no need for including this header. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20221109224250.2885119-1-dmitry.torokhov@gmail.com
2022-11-16arm: ptrace: user_regset_copyin_ignore() always returns 0Sergey Shtylyov1-5/+3
user_regset_copyin_ignore() always returns 0, so checking its result seems pointless -- don't do this anymore... Link: https://lkml.kernel.org/r/20221014212235.10770-3-s.shtylyov@omp.ru Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Cc: Brian Cain <bcain@quicinc.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: David S. Miller <davem@davemloft.net> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Helge Deller <deller@gmx.de> Cc: James Bottomley <James.Bottomley@HansenPartnership.com> Cc: Jonas Bonn <jonas@southpole.se> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Rich Felker <dalias@libc.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Stafford Horne <shorne@gmail.com> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Will Deacon <will@kernel.org> Cc: Yoshinori Sato <ysato@users.osdn.me> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2022-11-15ARM: dts: rockchip: disable arm_global_timer on rk3066 and rk3188Johan Jonker2-1/+7
The clock source and the sched_clock provided by the arm_global_timer on Rockchip rk3066a/rk3188 are quite unstable because their rates depend on the CPU frequency. Recent changes to the arm_global_timer driver makes it impossible to use. On the other side, the arm_global_timer has a higher rating than the ROCKCHIP_TIMER, it will be selected by default by the time framework while we want to use the stable Rockchip clock source. Keep the arm_global_timer disabled in order to have the DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/f275ca8d-fd0a-26e5-b978-b7f3df815e0a@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-11-14Merge tag 'ux500-dts-for-v6.2' of ↵Arnd Bergmann6-13/+44
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt Some Ux500 DTS updates for v6.2: - Some cleanups from Krzysztof for the SPI nodes. - Fix up the NFC chip in Janice. - Drop a bogus power domain regulator that isn't used for the crypto blocks. (We use proper power domains now.) - Add GPS to the Kyle. * tag 'ux500-dts-for-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: dts: ux500: Add GPS to the Kyle ARM: dts: DBx500 cryp and hash uses power domain ARM: dts: ux500: Fix up the Janice NFC chip ARM: dts: ste: ux500: align SPI node name with dtschema Link: https://lore.kernel.org/r/CACRpkdaXmmZWsGdTG5tqNragkoefcTeUHjR+ZwNyNaa0S7s-7Q@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14arm: dts: spear600: Add ssp controller nodesKory Maincent1-0/+30
The SPEAr600 has three Synchronous serial port to enables synchronous serial communication with slave or master peripherals (SPI). Lets add these nodes to be able to use them. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14arm: dts: spear600: Fix clcd interruptKory Maincent1-1/+1
Interrupt 12 of the Interrupt controller belongs to the SMI controller, the right one for the display controller is the interrupt 13. Fixes: 8113ba917dfa ("ARM: SPEAr: DT: Update device nodes") Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14arm: configs: spear6xx: Enable PL110 display controllerKory Maincent1-0/+2
Enable the PL110 DRM driver, used by the spear600. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14arm: configs: spear6xx: Refresh defconfigKory Maincent1-5/+0
Refresh the defconfig to follow the changes made over the year. I ensure important options have not gone away. I drop the gpio sysfs config as it is useless to keep it alone without CONFIG_EXPERT. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14Merge tag 'renesas-arm-soc-for-v6.2-tag1' of ↵Arnd Bergmann1-2/+0
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/soc Renesas ARM SoC updates for v6.2 - Drop selecting GPIOLIB and PINCTRL, which are already automatically selected as part of the SOC_RENESAS config option in drivers/soc/renesas/Kconfig. * tag 'renesas-arm-soc-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: renesas: Drop selecting GPIOLIB and PINCTRL ARM: shmobile: Drop selecting GPIOLIB and PINCTRL soc: renesas: Kconfig: Explicitly select GPIOLIB and PINCTRL config under SOC_RENESAS Link: https://lore.kernel.org/r/cover.1667558746.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14Merge tag 'at91-dt-6.2' of ↵Arnd Bergmann3-5/+82
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt AT91 DT for 6.2 It contains: - interrupt support for ethernet PHYs on pcb8290 board - thermal management support for SAMA7G5 by adding OTP controller (that keeps temperature sensor calibration data), proper ADC bindings and describing thermal zones - securam node from SAMA7G5 is now described with generic name (sram) - remove of status = "okay" from SAM9X60-EK regulators * tag 'at91-dt-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: at91: sam9x60ek: remove status = "okay" for regulators ARM: dts: at91: sama7g5: use generic name for securam ARM: dts: at91: sama7g5: add thermal zones node ARM: dts: at91: sama7g5: add temperature sensor ARM: dts: at91: sama7g5: add cells for temperature calibration ARM: dts: at91: sama7g5: add io-channel-cells to adc node ARM: dts: at91: sama7g5: add otpc node ARM: dts: lan966x: Add interrupt support for PHYs on pcb8290 Link: https://lore.kernel.org/r/20221110115431.180908-1-claudiu.beznea@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14Merge tag 'dt-cleanup-6.2' of ↵Arnd Bergmann56-277/+274
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt Minor improvements in ARM DTS for v6.2 1. Aspeed: fix qcom,dc-scm-v1-bmc compatible in the bindings. 2. Marvell: include bindings in maintainers entry. 3. Cleanup DTS according to bindings (panel endpoint unit address, incorrect spi-max-frequency, generic node names). 4. Few indentation fixes. * tag 'dt-cleanup-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt: dt-bindings: arm: aspeed: adjust qcom,dc-scm-v1-bmc compatible after rename ARM: dts: sunxi: correct indentation ARM: dts: omap: correct indentation ARM: dts: kirkwood: correct indentation ARM: dts: armada: correct indentation ARM: dts: ti: correct indentation ARM: dts: aspeed: align SPI node name with dtschema MAINTAINERS: ARM: marvell: include bindings ARM: dts: sunplus: sp7021: drop incorrect spi-max-frequency ARM: dts: am335x: drop panel endpoint unit address Link: https://lore.kernel.org/r/20221110092111.18581-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14ARM: findbit: add unwinder informationRussell King (Oracle)1-1/+7
Add unwinder information so oops in the findbit functions can create a proper backtrace. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-11-14ARM: findbit: operate by wordsRussell King (Oracle)2-34/+50
Convert the implementations to operate on words rather than bytes which makes bitmap searching faster. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-11-14ARM: findbit: convert to macrosRussell King (Oracle)1-116/+42
Since the pairs of _find_first and _find_next functions are pretty similar, use macros to generate this code. This commit does not change the generated code. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-11-14ARM: findbit: provide more efficient ARMv7 implementationRussell King (Oracle)1-1/+5
Provide a more efficient ARMv7 implementation to determine the first set bit in the supplied value. Signed-off-by: Russell King (Oracle) <rmk@armlinux.org.uk>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-26 22:10:34 +0300