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2021-06-01kprobes: Remove kprobe::fault_handlerPeter Zijlstra1-9/+0
The reason for kprobe::fault_handler(), as given by their comment: * We come here because instructions in the pre/post * handler caused the page_fault, this could happen * if handler tries to access user space by * copy_from_user(), get_user() etc. Let the * user-specified handler try to fix it first. Is just plain bad. Those other handlers are ran from non-preemptible context and had better use _nofault() functions. Also, there is no upstream usage of this. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> Link: https://lore.kernel.org/r/20210525073213.561116662@infradead.org
2021-06-01arm_pmu: Fix write counter incorrect in ARMv7 big-endian modeYang Jihong1-2/+2
Commit 3a95200d3f89 ("arm_pmu: Change API to support 64bit counter values") changes the input "value" type from 32-bit to 64-bit, which introduces the following problem: ARMv7 PMU counters is 32-bit width, in big-endian mode, write counter uses high 32-bit, which writes an incorrect value. Before: Performance counter stats for 'ls': 2.22 msec task-clock # 0.675 CPUs utilized 0 context-switches # 0.000 K/sec 0 cpu-migrations # 0.000 K/sec 49 page-faults # 0.022 M/sec 2150476593 cycles # 966.663 GHz 2148588788 instructions # 1.00 insn per cycle 2147745484 branches # 965435.074 M/sec 2147508540 branch-misses # 99.99% of all branches None of the above hw event counters are correct. Solution: "value" forcibly converted to 32-bit type before being written to PMU register. After: Performance counter stats for 'ls': 2.09 msec task-clock # 0.681 CPUs utilized 0 context-switches # 0.000 K/sec 0 cpu-migrations # 0.000 K/sec 46 page-faults # 0.022 M/sec 2807301 cycles # 1.344 GHz 1060159 instructions # 0.38 insn per cycle 250496 branches # 119.914 M/sec 23192 branch-misses # 9.26% of all branches Fixes: 3a95200d3f89 ("arm_pmu: Change API to support 64bit counter values") Cc: <stable@vger.kernel.org> Signed-off-by: Yang Jihong <yangjihong1@huawei.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20210430012659.232110-1-yangjihong1@huawei.com Signed-off-by: Will Deacon <will@kernel.org>
2021-06-01ARM: dts: stm32: fix timer nodes on STM32 MCU to prevent warningsAlexandre Torgue3-20/+0
Prevent warning seen with "make dtbs_check W=1" command: Warning (avoid_unnecessary_addr_size): /soc/timers@40001c00: unnecessary address-cells/size-cells without "ranges" or child "reg" property Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-06-01ARM: dts: stm32: fix RCC node name on stm32f429 MCUAlexandre Torgue1-1/+1
This prevent warning observed with "make dtbs_check W=1" Warning (simple_bus_reg): /soc/rcc@40023810: simple-bus unit address format error, expected "40023800" Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-06-01ARM: dts: stm32: fix gpio-keys node on STM32 MCU boardsAlexandre Torgue5-21/+11
Fix following warning observed with "make dtbs_check W=1" command. It concerns f429 eval and disco boards, f769 disco board. Warning (unit_address_vs_reg): /gpio_keys/button@0: node has a unit name, but no reg or ranges property Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-06-01ARM: dts: stm32: fix stm32mp157c-odyssey card detect pinGrzegorz Szymaszek1-1/+1
The microSD card detect pin is physically connected to the MPU pin PI3. The Device Tree configuration of the card detect pin was wrong—it was set to pin PB7 instead. If such configuration was used, the kernel would hang on “Waiting for root device” when booting from a microSD card. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-06-01ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151Patrice Chotard1-2/+2
Configure qspi's mdma from buffer transfer (max 128 bytes) to block transfer (max 64K bytes). mtd_speedtest shows that write throughtput increases : - from 734 to 782 KiB/s (~6.5%) with s25fl512s SPI-NOR. - from 4848 to 5319 KiB/s (~9.72%) with Micron SPI-NAND. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-06-01ARM: dts: stm32: Fix touchscreen node on dhcom-pdk2Marek Vasut1-2/+2
Fix make dtbs_check warning: arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dt.yaml:0:0: /soc/i2c@40015000/polytouch@38: failed to match any schema with compatible: ['edt,edt-ft5x06'] Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-06-01ARM: dts: stm32: Remove extra size-cells on dhcom-pdk2Marek Vasut1-2/+0
Fix make dtbs_check warning: arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dt.yaml: gpio-keys-polled: '#address-cells' is a dependency of '#size-cells' arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dt.yaml: gpio-keys: '#address-cells' is a dependency of '#size-cells' Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-05-31ARM: dts: qcom: Enable NAND + USB for RB3011Jonathan McDowell1-0/+58
Enable the NAND + USB devices for the MikroTik RB3011 platform now they're in the main IPQ806x DT. Signed-off-by: Jonathan McDowell <noodles@earth.li> Link: https://lore.kernel.org/r/1e5c89ba0d2491ca374f10e0446e21d0e42afd34.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-05-31ARM: dts: qcom: add L2CC and RPM for IPQ8064Jonathan McDowell1-0/+29
This adds the L2CC IPC resource and RPM devices to the IPQ8064 device tree. Tested on a Mikrotik RB3011. Signed-off-by: Jonathan McDowell <noodles@earth.li> Link: https://lore.kernel.org/r/a99eb2a27214b8f41070d7f1faec591e35666b21.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-05-31ARM: dts: qcom: Add USB port definitions to ipq806xJonathan McDowell1-0/+88
Signed-off-by: Jonathan McDowell <noodles@earth.li> Link: https://lore.kernel.org/r/ad2121defc539abdb339b23eef80a8930b5f086e.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-05-31ARM: dts: qcom: Add tsens details to ipq806xJonathan McDowell1-0/+241
Signed-off-by: Jonathan McDowell <noodles@earth.li> Link: https://lore.kernel.org/r/f7ebf47ca9e7e973e696e6b9b4fff3a2ac5da40d.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-05-31ARM: dts: qcom: Add ADM DMA + NAND definitions to ipq806xJonathan McDowell1-0/+67
Now the ADM driver is in mainline add the appropriate definitions for it and the NAND controller to get NAND working on IPQ806x platforms, Signed-off-by: Jonathan McDowell <noodles@earth.li> Link: https://lore.kernel.org/r/17f88a26860f5976ad08dd3c12ea079ba474b6fd.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-05-31ARM: dts: exynos: Disable unused camera input for I9100Timon Baetz1-2/+4
As the back camera is not implemented disable the second pair of fimc child nodes as they are not functional. This prevents creating the associated /dev/videoX devices. Signed-off-by: Timon Baetz <timon.baetz@protonmail.com> Link: https://lore.kernel.org/r/20210530105535.4165-1-timon.baetz@protonmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-05-31ARM: dts: stm32: Rework LAN8710Ai PHY reset on DHCOM SoMMarek Vasut1-1/+7
The Microchip LAN8710Ai PHY requires XTAL1/CLKIN external clock to be enabled when the nRST is toggled according to datasheet Microchip LAN8710A/LAN8710Ai DS00002164B page 35 section 3.8.5.1 Hardware Reset: " A Hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held low for the minimum time detailed in Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on page 59 to ensure a proper transceiver reset. During a Hardware reset, an external clock must be supplied to the XTAL1/CLKIN signal. " This is accidentally fulfilled in the current setup, where ETHCK_K is used to supply both PHY XTAL1/CLKIN and is also fed back through eth_clk_fb to supply ETHRX clock of the DWMAC. Hence, the DWMAC enables ETHRX clock, that has ETHCK_K as parent, so ETHCK_K clock are also enabled, and then the PHY reset toggles. However, this is not always the case, e.g. in case the PHY XTAL1/CLKIN clock are supplied by some other clock source than ETHCK_K or in case ETHRX clock are not supplied by ETHCK_K. In the later case, ETHCK_K would be kept disabled, while ETHRX clock would be enabled, so the PHY would not be receiving XTAL1/CLKIN clock and the reset would fail. Improve the DT by adding the PHY clock phandle into the PHY node, which then also requires moving the PHY reset GPIO specifier in the same place and that then also requires correct PHY reset GPIO timing, so add that too. A brief note regarding the timing, the datasheet says the reset should stay asserted for at least 100uS and software should wait at least 200nS after deassertion. Set both delays to 500uS which should be plenty. Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-05-31ARM: tegra_defconfig: Enable CONFIG_DEVFREQ_THERMALDmitry Osipenko1-0/+1
Memory-related Tegra devfreq devices now could be used as a cooling devices. Enable CONFIG_DEVFREQ_THERMAL by default since this option enables cooling functionality of the devfreq drivers. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: dts: sun8i: v3s: enable emac for zero DockAndreas Rehn1-4/+13
dwmac-sun8i supports v3s and Licheepi-zero Dock provides an ethernet port furthermore, align nodes in alphabetical order Signed-off-by: Andreas Rehn <rehn.andreas86@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210525173159.183415-1-rehn.andreas86@gmail.com
2021-05-31ARM: tegra: ouya: Enable memory frequency thermal throttling using ACTMONDmitry Osipenko1-1/+3
The ACTMON module monitors activity of memory clients and then devfreq driver makes decisions about a required memory frequency based on info from ACTMON. Add ACTMON device to the thermal zone of Ouya in order to use it as a cooling device which throttles memory freq on overheat. Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Matt Merhar <mattmerhar@protonmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: tegra: nexus7: Enable memory frequency thermal throttling using ACTMONDmitry Osipenko1-1/+3
The ACTMON module monitors activity of memory clients and then devfreq driver makes decisions about a required memory frequency based on info from ACTMON. Add ACTMON device to the thermal zone of Nexus 7 in order to use it as a cooling device which throttles memory freq on overheat. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: tegra: Add cooling cells to ACTMON device-tree nodeDmitry Osipenko2-2/+4
The ACTMON module monitors activity of memory clients and decisions about a minimum required memory frequency are made based on info from ACTMON. Add cooling cells to ACTMON device-tree node in order to turn it into a cooling device that will throttle memory freq on overheat. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: tegra: nexus7: Correct 3v3 regulator GPIO of PM269 variantDmitry Osipenko1-1/+1
The 3v3 regulator GPIO is GP6 and not GP7, which is the DDR regulator. Both regulators are always-on, nevertheless the DT model needs to be corrected, fix it. Reported-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: tegra: nexus7: Remove monitored-battery propertyDmitry Osipenko1-1/+0
The bq27541 Linux kernel driver will try to reprogram controller based on the values from monitored-battery node, but it fails to do so because controller was locked by manufacturer. Still this is a very undesirable behaviour, hence let's remove the optional battery node. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: tegra: nexus7: Improve thermal zonesDmitry Osipenko1-9/+2
Remove unused thermal zone just to clean up device-tree and set critical temperature further apart from the passive cooling trip point since during or thermal testing of Asus Transformer devices we found that CPU could reach the critical temperature in a certain kernel configurations for a brief moment if critical trip point is set close to the passive trip point and then device will be immediately shut off without getting a chance to cool down using passive cooling. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: tegra: nexus7: Add i2c-thermtrip nodeDmitry Osipenko2-0/+18
Add i2c-thermtrip node which enables emergency shutdown by PMC on SoC die overheat detected by TSENSOR. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: tegra: paz00: Add CPU thermal zoneDmitry Osipenko1-2/+40
Add thermal zone with a passive cooling trip for CPU. Attach it to the LM90 sensor which monitors CPU temperature. Now CPU frequencies will be throttled once trip point is reached, preventing critical overheat. Tested-by: Agneli <poczt@protonmail.ch> Tested-by: Paul Fertser <fercerpav@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: tegra: wm8903: Fix polarity of headphones-detection GPIO in device-treesDmitry Osipenko8-8/+8
All Tegra boards which use WM8903 audio codec are specifying a wrong polarity for the headphones detection GPIO. The kernel driver hardcodes the polarity to active-low, which is the correct polarity, so we can fix the device-trees safely. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: tegra: Add reg property to Tegra20 EMC table device-tree nodesDmitry Osipenko2-0/+5
The reg property is now specified for the emc-tables nodes in the Tegra20 device-tree binding. Add reg property to the EMC table device-tree nodes of Tegra20 board device-trees in order to silence dt_binding_check warning about the missing property. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: tegra: acer-a500: Bump thermal trips by 10CDmitry Osipenko1-4/+4
It's possible to hit the temperature of the thermal zone in a very warm environment under a constant load, like watching a video using software decoding. It's even easier to hit the limit with a slightly overclocked CPU. Bump the temperature limit by 10C in order to improve user experience. Acer A500 has a large board and 10" display panel which are used for the heat dissipation, the SoC is placed far away from battery, hence we can safely bump the temperature limit. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: tegra: acer-a500: Specify proper voltage for WiFi SDIO busDmitry Osipenko1-1/+1
Tegra20 has v2.00 SDMMC controller which doesn't support voltage switching and the WiFi SDIO bus voltage is fixed to 1.8v in accordance to the board's schematics, while MMC core confusingly saying that it's 3.3v because of the v2.00. Let's correct the voltage in the device-tree just for consistency. This is a minor improvement which doesn't fix any problems. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: tegra: acer-a500: Improve microphone detectionDmitry Osipenko1-1/+4
Use edge-triggered interrupt and set delay to 100ms for microphone hook detection. This doesn't fix any known problems, but there is a smaller chance to miss insertion of the microphone now, which previously happened rarely. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31ARM: dts: silk: Configure pull-up for SOFT_SW GPIO keysGeert Uytterhoeven1-1/+9
The GPIO pins connected to the 4 Software Switches ("SOFT_SW", SW12) do not have external pull-up resistors, but rely on internal pull-ups being enabled. Fortunately this is satisfied by the initial state of these pins. Make this explicit by enabling bias-pull-up, to remove the dependency on initial state and/or boot loader configuration. While at it, rename the surrounding device node from "gpio-keys" to "keyboard", to comply with generic node name recommendations. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/45f38a5333feba9bea80efeb5a41a6c3f60deda2.1619785905.git.geert+renesas@glider.be
2021-05-31ARM: dts: gose: Configure pull-up for SOFT_SW GPIO keysGeert Uytterhoeven1-1/+9
The GPIO pins connected to the 4 Software Switches ("SOFT_SW", SW2) do not have external pull-up resistors, but rely on internal pull-ups being enabled. Fortunately this is satisfied by the initial state of these pins. Make this explicit by enabling bias-pull-up, to remove the dependency on initial state and/or boot loader configuration. While at it, rename the surrounding device node from "gpio-keys" to "keyboard", to comply with generic node name recommendations. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1cdec892b1491309b12bdaf7bc8428b3a19b1ed5.1619785905.git.geert+renesas@glider.be
2021-05-31ARM: dts: blanche: Configure pull-up for SOFT_SW and SW25 GPIO keysGeert Uytterhoeven1-0/+8
The GPIO pins connected to the 4 Software Switches (SW2) and the second Tact Switch (SW25) do not have external pull-up resistors, but rely on internal pull-ups being enabled. Fortunately this is satisfied by the initial state of these pins. Make this explicit by enabling bias-pull-up, to remove the dependency on initial state and/or boot loader configuration. Note that the GPIO pin connected to the first Tact Switch (SW24) does have an external pull-up resistor. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/011e4c461767f2dd690b655b3dd501eb554184c1.1619785905.git.geert+renesas@glider.be
2021-05-31ARM: dts: lager: Configure pull-up for SOFT_SW GPIO keysGeert Uytterhoeven1-0/+8
The GPIO pins connected to the 4 Software Switches (SW2) do not have external pull-up resistors, but rely on internal pull-ups being enabled. Fortunately this is satisfied by the initial state of these pins. Make this explicit by enabling bias-pull-up, to remove the dependency on initial state and/or boot loader configuration. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/9fae3c0c2c0000f6b43c9ce87fe64a594b30a7da.1619785905.git.geert+renesas@glider.be
2021-05-31Merge 5.13-rc4 into usb-nextGreg Kroah-Hartman3-2/+8
We need the usb/thunderbolt fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-05-29ARM: dts: qcom: sdx55-telit: Represent secure-regions as 64-bit elementsManivannan Sadhasivam1-2/+2
The corresponding MTD code expects the regions to be of 64-bit elements. Hence, prefix "/bits/ 64", otherwise the regions will not be parsed correctly. Fixes: 6a5d3c611930 ("ARM: dts: qcom: sdx55: Add basic devicetree support for Telit FN980 TLB") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210512050141.43338-2-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-05-29ARM: dts: qcom: sdx55-t55: Represent secure-regions as 64-bit elementsManivannan Sadhasivam1-1/+1
The corresponding MTD code expects the regions to be of 64-bit elements. Hence, prefix "/bits/ 64", otherwise the regions will not be parsed correctly. Fixes: 3263d4be5788 ("ARM: dts: qcom: sdx55: Add basic devicetree support for Thundercomm T55") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210512050141.43338-1-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-05-28ARM: dts: rockchip: move mmc aliases to board dts on rk3066/rk3188Johan Jonker8-3/+35
As suggested by Arnd Bergmann, the newly added mmc aliases should be board specific, so move them from the general dtsi to the individual boards. Suggested-by: Arnd Bergmann <arnd@kernel.org> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210520091822.28491-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-05-27ARM: dts: alt: Add SW2 as GPIO keysWolfram Sang1-0/+42
SW2 on Alt is connected as on Lager board. So, use the same GPIO settings. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210525091512.29119-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-05-27ARM: dts: OMAP2+: Replace underscores in sub-mailbox node namesSuman Anna8-20/+20
A number of sub-mailbox node names in various OMAP2+ dts files are currently using underscores. This is not adhering to the node name convention, fix all of these to use hiphens. These nodes are already using the prefix mbox, so they will be in compliance with the sub-mailbox node name convention being added in the OMAP Mailbox YAML binding as well. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-05-27ARM: dts: AM33xx/AM43xx: Rename wkup_m3 sub-mailbox nodeSuman Anna2-2/+2
The OMAP sub-mailbox used to communicate with the Wakeup M3 remote processor is currently named wkup_m3. This name can be confused with the remote processor node. So, rename this to mbox-wkup-m3 to remove the ambiguity and to also adhere to the sub-mailbox node name convention being added in the OMAP Mailbox YAML binding. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-05-27ARM: dts: OMAP2/OMAP3: Rename processor sub-mailbox nodesSuman Anna3-4/+4
The OMAP sub-mailbox used to communicate with the DSP and IVA remote processors are currently named after the processor name. These can be confused with the remote processors themselves. Rename them to remove the ambiguity and use the prefix mbox to also adhere to the sub-mailbox node name convention being added in the OMAP Mailbox YAML binding. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-05-27ARM: dts: OMAP2420: Drop interrupt-names from mailbox nodeSuman Anna1-1/+0
The interrupt-names property is neither defined nor used in either of the OMAP Mailbox binding or the driver. So, drop them. This is in preparation for converting the OMAP Mailbox binding to YAML format. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-05-27ARM: dts: am437x-l4: Drop ti,omap2-uart entry from UART nodesVignesh Raghavendra1-6/+6
ti,omap2-uart was kept around to work with legacy omap-serial driver. Now that we have completed move to 8250-omap.c drop legacy compatible. This will simplify writing YAML schema. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-05-27ARM: dts: dra7-l4: Drop ti,omap4-uart entry from UART nodesVignesh Raghavendra1-10/+10
ti,omap4-uart was kept around to work with legacy omap-serial driver. Now that we have completed move to 8250-omap.c drop legacy compatible. This will simplify writing YAML schema. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-05-27ARM: dts: am335x: fix ti,no-reset-on-init flag for gpiosGrygorii Strashko5-6/+6
The ti,no-reset-on-init flag need to be at the interconnect target module level for the modules that have it defined. The ti-sysc driver handles this case, but produces warning, not a critical issue. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-05-27ARM: dts: am437x-gp-evm: fix ti,no-reset-on-init flag for gpiosGrygorii Strashko2-2/+5
The ti,no-reset-on-init flag need to be at the interconnect target module level for the modules that have it defined. The ti-sysc driver handles this case, but produces warning, not a critical issue. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-05-27ARM: dts: am57xx-cl-som-am57x: fix ti,no-reset-on-init flag for gpiosGrygorii Strashko2-5/+4
The ti,no-reset-on-init flag need to be at the interconnect target module level for the modules that have it defined. The ti-sysc driver handles this case, but produces warning, not a critical issue. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-05-27ARM: dts: dra7x-evm: Align GPIO hog names with dt-schemaGeert Uytterhoeven4-4/+4
The dt-schema for nxp,pcf8575 expects GPIO hogs node names to end with a 'hog' suffix. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 13:20:08 +0300