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2015-06-11Merge branch 'socfpga/soc' into next/socKevin Hilman7-6/+342
* socfpga/soc: ARM: socfpga: support suspend to ram ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
2015-06-11ARM: socfpga: support suspend to ramAlan Tull6-3/+305
Add code that requests that the sdr controller go into self-refresh mode. This code is run from ocram. Suspend-to-RAM and EDAC support are mutually exclusive on SOCFPGA. If the EDAC is enabled, it will prevent the platform from going into suspend. Example of how to request to suspend to ram: $ echo enabled > \ /sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup $ echo -n mem > /sys/power/state Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-11ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10Dinh Nguyen2-0/+34
Add boot_secondary implementation for the Arria10 platform. Bringing up the secondary core on the Arria 10 platform is pretty similar to the Cyclone/Arria 5 platform, with the exception of the following differences: - Register offset to bringup CPU1 out of reset is different. - The cpu1-start-addr for Arria10 contains an additional nibble. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-11ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5Dinh Nguyen3-3/+3
Convert cyclone5/arria5 to use CPU_METHOD_OF_DECLARE for smp operations. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-01ARM: Kconfig: Select clocksource in STM32 entryMaxime Coquelin1-0/+1
STM32 clocksource driver needs to be selected if ARCH_STM32. Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-06-01Merge tag 'arm-soc/for-4.2/soc-part2' of http://github.com/broadcom/stblinux ↵Arnd Bergmann3-2/+5
into next/soc Merge "changes for Broadcom SoCs": - Dan fixes an error path in the BCM63xx SMP code - Ray adds the relevant Kconfig selects to enable the Broadcom NAND driver on Cygnus - Kevin provides a change to the Broadcom GISB arbiter driver to make it work with MIPS-based big-endian STB SoCs (this was a long-standing change that had dependencies on code in drivers/of/*) - Gregory enables the use of GPIOLIB for brcmstb SoCs and bumps the number of GPIOs for these platforms * tag 'arm-soc/for-4.2/soc-part2' of http://github.com/broadcom/stblinux: ARM: brcmstb: Add default gpio number ARM: brcmstb: Select ARCH_WANT_OPTIONAL_GPIOLIB bus: brcmstb_gisb: Honor the "big-endian" and "native-endian" DT properties ARM: BCM: Enable NAND support for iProc SoCs ARM: BCM63xx: fix an error path in bcm63xx_pmb_power_on_cpu()
2015-05-30ARM: brcmstb: Add default gpio numberGregory Fong1-1/+2
Out of the brcmstb SoCs that I know, BCM3390 has the largest numbers of GPIOs, with its - 320 "peripheral" GPIOs - 5*32 = 160 UPG GPIOs (counting unused lines, which do get counted) - 2*32 = 64 UPG AON GPIOs (counting unused lines) Total: 544 I suspect that the upper limit will only need to be higher in the future, so set it to 1024. Signed-off-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-05-30ARM: brcmstb: Select ARCH_WANT_OPTIONAL_GPIOLIBGregory Fong1-0/+1
Select ARCH_WANT_OPTIONAL_GPIOLIB from BRCMSTB to allow GPIOLIB and GPIO_BRCMSTB to be enabled. Signed-off-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-05-29Merge tag 'renesas-soc-for-v4.2' of ↵Arnd Bergmann1-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Merge "Renesas ARM Based SoC Updates for v4.2" from Simon Horman: * Only select sound drivers that build * tag 'renesas-soc-for-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: only select sound drivers that build
2015-05-29ARM: BCM: Enable NAND support for iProc SoCsRay Jui1-0/+1
Select CONFIG_MTD_NAND_BRCMNAND for all iProc SoCs Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-05-27ARM: BCM63xx: fix an error path in bcm63xx_pmb_power_on_cpu()Dan Carpenter1-1/+1
We need to unlock and unmap some resourses before returning. Fixes: 3f2a43c98d72 ('ARM: BCM63xx: Add secondary CPU PMB initialization sequence') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-05-25ARM: shmobile: only select sound drivers that buildArnd Bergmann1-2/+2
A couple of codec drivers are selected by shmobile platform code, but depend on I2C, which results in a build error: sound/soc/codecs/ak4642.c:638:1: warning: data definition has no type or storage class module_i2c_driver(ak4642_i2c_driver); ^ sound/soc/codecs/ak4642.c:638:1: error: type defaults to 'int' in declaration of 'module_i2c_driver' [-Werror=implicit-int] sound/soc/codecs/ak4642.c:638:1: warning: parameter names (without types) in function declaration sound/soc/codecs/ak4642.c:627:26: warning: 'ak4642_i2c_driver' defined but not used [-Wunused-variable] This ensures that we do not enable the respective drivers when I2C is disabled. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-05-22ARM: use ARM_SINGLE_ARMV7M for ARMv7-M platformsStefan Agner3-59/+33
Use the new config symbol ARM_SINGLE_ARMV7M which groups config symbols used by modern ARMv7-M platforms. This allows supporting multiple ARMv7-M platforms in one kernel image. However, a common kernel image requires the combined platforms to share the same main memory layout to be bootable. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Joachim Eastwood <manabian@gmail.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-22ARM: zx: fix building with CONFIG_THUMB2_KERNELArnd Bergmann1-0/+1
The newly added zx platform causes a build error when CONFIG_THUMB2_KERNEL is enabled: arch/arm/mach-zx/headsmp.S:16: Error: invalid immediate for address calculation (value = 0x00000004) I'm assuming that the ROM code that is calling these entry points runs in ARM mode, so there would be another problem in the same file, and we can solve both problems at once by adding a '.arm' statement that will make zx_resume_jump and zx_secondary_startup both be built as ARM code. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jun Nie <jun.nie@linaro.org> Tested-by: Jun Nie <jun.nie@linaro.org>
2015-05-22Merge tag 'omap-for-v4.2/omap1-v2' of ↵Arnd Bergmann34-185/+203
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc Merge fixed up omap1 sparse irq support for v4.2 from Tony Lindgren: Add support for CONFIG_SPARSE_IRQ for omap1. This takes us a bit closer to making omap1 support multiarch. After this series we still need to make omap1 use the common clock framework and fix up the drivers to not rely on includes from mach and plat directories. Note that this branch depends on a GPIO driver fix in v4.1-rc3 d2d05c65c40e ("gpio: omap: Fix regression for MPUIO interrupts"). * tag 'omap-for-v4.2/omap1-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP1: Fix section mismatch warnings for omap_cfg_reg ARM: OMAP1: Fix randconfig builds if ARCH_OMAP15XX not selected ARM: OMAP1: Change interrupt numbering for sparse IRQ ARM: omap1: Switch to use MULTI_IRQ ARM: OMAP1: Switch to use generic irqchip in preparation for sparse IRQ ARM: OMAP1: Move UART defines to prepare for sparse IRQ
2015-05-22Merge tag 'arm-soc/for-4.2/soc-take2' of http://github.com/broadcom/stblinux ↵Arnd Bergmann8-5/+455
into next/soc Merge mach-bcm changes from Florian Fainelli: This pull request contains the following changes: - Rafal adds an additional fault code to be ignored by the kernel on BCM5301X SoC - BCM63138 SMP support which: * common code to control the PMB bus, to be shared with a reset controller driver in drivers/reset * secondary CPU initialization sequence using PMB helpers * small changes suggested by Russell King to allow platforms to disable VFP * tag 'arm-soc/for-4.2/soc-take2' of http://github.com/broadcom/stblinux: ARM: BCM63xx: Add SMP support for BCM63138 ARM: vfp: Add vfp_disable for problematic platforms ARM: vfp: Add include guards ARM: BCM63xx: Add secondary CPU PMB initialization sequence ARM: BCM63xx: Add Broadcom BCM63xx PMB controller helpers ARM: BCM5301X: Ignore another (BCM4709 specific) fault code
2015-05-22ARM: OMAP1: Fix section mismatch warnings for omap_cfg_regTony Lindgren1-4/+4
This is cleary used after init time too for example for configuring UART wake-up events during runtime. This fixes section mismatch warnings for randconfig builds that happen because __init_or_module. Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-05-22ARM: OMAP1: Fix randconfig builds if ARCH_OMAP15XX not selectedTony Lindgren7-1/+12
With the omap1 SPARSE_IRQ changes mach/irqs.h is no longer automatically included. Turns out now we rely on ARCH_OMAP15XX including hardware.h from memory.h, so without ARCH_OMAP15XX we get build failures. As we have legacy drivers still relying on these indirect includes, let's not add more mach includes to the drivers. Those have to be removed anyways for multiplatform support. Let's fix up mach-omap1 to include soc.h where cpu_is_omap checks are done, and common.h for board-*.c files. But let's keep the indirect memory.h include for now to avoid unnecessary churn in the drivers. Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-05-21ARM: BCM63xx: Add SMP support for BCM63138Florian Fainelli4-1/+207
Add support for booting the secondary CPU on BCM63138, this involves: - locating the bootlut to write the reset vector - powering up the second CPU when we need to using the DT-supplied PMB references - disabling VFP when enabled such that we can keep having SMP Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-05-21ARM: vfp: Add vfp_disable for problematic platformsFlorian Fainelli2-0/+17
Some platforms might not be able to fully utilize VFP when e.g: one CPU out of two in a SMP complex lacks a VFP unit. Adding code to migrate task to the CPU which has a VFP unit would be cumbersome and not performant, instead, just add the ability to disable VFP. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-05-21ARM: vfp: Add include guardsFlorian Fainelli1-0/+5
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-05-21ARM: BCM63xx: Add secondary CPU PMB initialization sequenceFlorian Fainelli1-0/+221
The sequence to initialize a secondary CPU using the BCM63138 PMB is extremely specific and represents much more code than any other on-chip peripheral (AHCI, USB 3.0 or integrated Ethernet switch), as such we keep that code local and utilize Device Tree to lookup all the resources we need from the CPU device tree node. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-05-21ARM: vf610: enable Cortex-M4 configuration on Vybrid SoCStefan Agner3-17/+22
This patch allows to build the Kernel for Vybrid (VF6xx) SoC when ARMv7-M CPU is selected. The resulting image runs on the secondary Cortex-M4 core. This core has equally access to all peripherals as the main Cortex-A5 core. However, there is no resource control mechanism, hence when both cores are used simultaneously, orthogonal device tree's are required. The boot CPU is dependent on the SoC variant. The available boards use mostly variants where the Cortex-A5 is the primary and hence the boot CPU. Booting the secondary Cortex-M4 CPU needs SoC specific registers written. There is no in kernel support for this right now, a external userspace utility called "m4boot" can be used to boot the kernel: m4boot xipImage initramfs.cpio.lzo vf610m4-colibri.dtb Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-21ARM: introduce ARM_SINGLE_ARMV7M for ARMv7-M platformsStefan Agner2-2/+16
This introduces a new top level config symbol ARM_SINGLE_ARMV7M for non-MMU, ARMv7-M platforms. It also support multiple ARMv7-M platforms in one kernel image since the cores share the same basic memory layout and interrupt controller. However, this works only if the combined platforms also have a similar (main) memory layout. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-21ARM: unify MMU/!MMU addruart callsStefan Agner2-2/+2
Remove the needless differences between MMU/!MMU addruart calls. This allows to use the same addruart macro on SoC level. Useful for SoC consisting of multiple CPUs with and without MMU such as Freescale Vybrid. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-21ARM: BCM5301X: Ignore another (BCM4709 specific) fault codeRafał Miłecki1-4/+5
Broadcom ARM devices seem to generate some fault once per boot. We already have an ignoring handler for BCM4707/BCM4708, but BCM4709 generates different code. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2015-05-20ARM: OMAP1: Change interrupt numbering for sparse IRQTony Lindgren9-71/+75
Change interrupt numbering for sparse IRQ. We do this using a fixed offset until we can drop irqs.h once all it's users have been updated. Note that this depends on the GPIO fix for the MPUIO IRQs "gpio: omap: Fix regression for MPUIO interrupts". Also note that this patch adds some extra irq alloc warnings that will go away when we stop calling irq_alloc_descs in gpio-omap.c with a follow-up patch. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-05-20ARM: omap1: Switch to use MULTI_IRQTony Lindgren19-47/+53
This allows us to get a bit further with SPARSE_IRQ and MULTIARCH support. Note that we now also rename omap_irq_flags to omap_l2_irq as that's the omap_irq_flags naming is confusing. It just contains the interrupt number for the l2 irq. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-05-20ARM: OMAP1: Switch to use generic irqchip in preparation for sparse IRQTony Lindgren1-58/+60
Let's set up things ready for enabling sparse IRQ and remove the omap_read/write usage. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-05-20ARM: OMAP1: Move UART defines to prepare for sparse IRQTony Lindgren1-5/+0
These have been indirectly included via asm/irqs.h that has included mach/hardware.h unless SPARSE_IRQ is specified. Let's move them to where the other OMAP serial defines for 8250 are. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-05-20Merge tag 'zynq-soc-for-4.2' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann3-16/+19
next/soc Merge "arm: Xilinx Zynq SoC patches for v4.2" from Michal Simek: - Change SoC reset path - Fix SLCR unlock scheme * tag 'zynq-soc-for-4.2' of https://github.com/Xilinx/linux-xlnx: ARM: zynq: Drop use of slcr_unlock in zynq_slcr_system_restart ARM: zynq: Use restart_handler mechanism for slcr reset
2015-05-20ARM: uniphier: only select TWD for SMPArnd Bergmann1-1/+1
This makes uniphier behave like all the other platforms that support TWD, and only select this driver when SMP is enabled. Without this, we get a compile error on UP builds: arch/arm/kernel/smp_twd.c: In function 'twd_local_timer_of_register': arch/arm/kernel/smp_twd.c:391:20: error: 'setup_max_cpus' undeclared (first use in this function) Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-20ARM: lpc18xx: define low-level debug symbol for LPC18xx/43xxJoachim Eastwood1-1/+9
Using a dedicated symbol for low-level debugging instead of the arch symbol will make this platform play nice when enabled on a kernel that supports multiple platforms. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-18ARM: zynq: Drop use of slcr_unlock in zynq_slcr_system_restartJosh Cartwright1-7/+0
The SLCR is unconditionally unlocked early on boot in zynq_slcr_init() and not ever re-locked. As such, it is not necessary to explicitly unlock in the restart codepath. Signed-off-by: Josh Cartwright <joshc@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-05-18ARM: zynq: Use restart_handler mechanism for slcr resetJosh Cartwright3-9/+19
By making use of the restart_handler chain mechanism, the SLCR-based reset mechanism can be prioritized amongst other mechanisms available on a particular board. Choose a default high-ish priority of 192 for this restart mechanism. Signed-off-by: Josh Cartwright <joshc@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-05-15ARM: zx: enable SMP and hotplug for zx296702Jun Nie4-0/+241
Bring up the secondary core. Enable hotplug with supporting powering off secondary core. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-15ARM: zx: add low level debug support for zx296702Jun Nie2-0/+21
Use the UART0 peripheral for low level debug. Only the UART port 0 is currently supported. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-15ARM: zx: add basic support for ZTE ZX296702Jun Nie5-0/+47
Add basic code for ZTE ZX296702 platform. [arnd: removed unused zx296702_init_machine function, and changed l2c aux val to default] Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-15ARM: lpc18xx: add basic support for NXP LPC18xx/43xx SoCsJoachim Eastwood6-1/+49
Add support for NXP's LPC18xx (Cortex-M3) and LPC43xx (Cortex-M4) SoCs. These SoCs are NXP's high preformance MCU line and can run at clock speeds up to 180 MHz for LPC18xx and 204 MHz for LPC43xx. LPC43xx is more or less a LPC18xx with a Cortex-M4F core and a few extra peripherals. The LPC43xx series also features one or two Cortex-M0 cores that can be used to offload the main M4 core. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-15ARM: Add STM32 family machineMaxime Coquelin5-0/+42
STMicrolectronics's STM32 series is a family of Cortex-M microcontrollers. It is used in various applications, and proposes a wide range of peripherals. Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-15Merge tag 'pxa-for-4.2' of https://github.com/rjarzmik/linux into next/socArnd Bergmann18-908/+33
Merge "pxa changes for v4.2 cycle" from Robert Jarzmik: The main and only feature is the conversion of all pxa variants to clock framework. This encompasses pxa25x, pxa27x and pxa3xx, for all boards. This should be a disruptive cycle in the normally quiet pxa history, as the change can break any platform, and the test were performed on only 4 boards (lubbock, zylonite, mioa701, cm-x300). * tag 'pxa-for-4.2' of https://github.com/rjarzmik/linux: ARM: pxa: Constify irq_domain_ops ARM: pxa: Transition pxa25x, pxa27x, pxa3xx to clk framework ARM: pxa: convert eseries to clock framework ARM: pxa: Transition pxa25x and pxa27x to clk framework ARM: pxa: pxa27x skip default device initialization with DT clk: pxa: add missing pxa27x clocks for Irda and sa1100-rtc ARM: pxa: move gpio11 clock to board files ARM: pxa: change clocks init sequence
2015-05-15Merge tag 'rpi-soc-for-armsoc-v4.2' of ↵Arnd Bergmann1-91/+0
git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi into next/soc Merge "RaspberryPi SoC (mach) changes due for v4.2" from Lee Jones: * tag 'rpi-soc-for-armsoc-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi: ARM: bcm2835: Move the restart/power_off handling to the WDT driver ARM: bcm2835: Drop the init_irq() hook ARM: bcm2835: Skip doing our own iotable_init() initialization
2015-05-14ARM: bcm2835: Move the restart/power_off handling to the WDT driverEric Anholt1-73/+0
Since the WDT is what's used to drive restart and power off, it makes more sense to keep it there, where the regs are already mapped and definitions for them provided. Note that this means you may need to add CONFIG_BCM2835_WDT to retain functionality of your kernel. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-05-14ARM: bcm2835: Drop the init_irq() hookEric Anholt1-1/+0
This is the default function that gets called if the hook is NULL. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-05-14ARM: bcm2835: Skip doing our own iotable_init() initializationEric Anholt1-17/+0
The only thing we were using this 16MB mapping of IO peripherals for was the uart's early debug mapping. If we just drop the map_io hook, the kernel will call debug_ll_io_init() for us, which maps the single page needed for the device. Signed-off-by: Eric Anholt <eric@anholt.net> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-05-13Merge tag 'tegra-for-4.2-soc' of ↵Arnd Bergmann6-23/+38
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc Merge "ARM: tegra: Core SoC changes for v4.2-rc1" from Thierry Reding: A couple of changes to the core SoC support code. Perhaps the most important part is a fix for a regression in LP1 suspend/resume code that was introduced a while back. * tag 'tegra-for-4.2-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: move to using a restart handler ARM: tegra20: Store CPU "resettable" status in IRAM soc/tegra: Watch wait_for_completion_timeout() return type
2015-05-13Merge tag 'socfpga_updates_for_v4.2' of ↵Arnd Bergmann7-66/+37
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/soc Merge "SoCFPGA updates for v4.2" from Dinh Nguyen: - Add big endian support - Add earlyprintk support on UART1 that is used on Arria10 - Remove the need to map uart_io_desc - Use of_iomap to map the SCU - Remove socfpga_smp_init_cpus as arm_dt_init_cpu_maps is already doing the CPU mapping. * tag 'socfpga_updates_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: use of_iomap to map the SCU ARM: socfpga: remove the need to map uart_io_desc ARM: socfpga: Add support for UART1 debug uart for earlyprintk ARM: socfpga: support big endian for socfpga ARM: socfpga: enable big endian for secondary core(s) ARM: debug: fix big endian operation for 8250 word mode
2015-05-13ARM: socfpga: use of_iomap to map the SCUDinh Nguyen3-49/+10
Use of_iomap to map the "arm,cortex-a9-scu". By doing this, we can remove map_io in socfpga.c. Also, we can remove socfpga_smp_init_cpus, as arm_dt_init_cpu_maps is already doing the CPU mapping. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-13ARM: pxa: Constify irq_domain_opsKrzysztof Kozlowski1-1/+1
The irq_domain_ops are not modified by the driver and the irqdomain core code accepts pointer to a const data. Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2015-05-13ARM: pxa: Transition pxa25x, pxa27x, pxa3xx to clk frameworkRobert Jarzmik16-528/+6
Transition the PXA25x, PXA27x and PXA3xx CPUs to the clock framework. This transition still enables legacy platforms to run without device tree as before, ie relying on platform data encoded in board specific files. This is the last step of clock framework transition for pxa platforms. It was tested on lubbock (pxa25x), mioa701 (pxa27x) and zylonite (pxa3xx). Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
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