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2020-09-16efi/libstub: arm32: Base FDT and initrd placement on image addressArd Biesheuvel1-3/+2
The way we use the base of DRAM in the EFI stub is problematic as it is ill defined what the base of DRAM actually means. There are some restrictions on the placement of FDT and initrd which are defined in terms of dram_base, but given that the placement of the kernel in memory is what defines these boundaries (as on ARM, this is where the linear region starts), it is better to use the image address in these cases, and disregard dram_base altogether. Reviewed-by: Maxim Uvarov <maxim.uvarov@linaro.org> Tested-by: Maxim Uvarov <maxim.uvarov@linaro.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
2020-09-16Merge branch 'kvm-arm64/nvhe-hyp-context' into kvmarm-master/nextMarc Zyngier19-271/+572
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-09-16arm64: dts: sparx5: Add spi-nand devicesLars Povlsen5-0/+67
This patch add spi-nand DT nodes to the applicable Sparx5 boards. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-7-lars.povlsen@microchip.com
2020-09-16arm64: dts: sparx5: Add spi-nor supportLars Povlsen3-0/+80
This add spi-nor device nodes to the Sparx5 reference boards. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-6-lars.povlsen@microchip.com
2020-09-16arm64: dts: sparx5: Add SPI controller and associated mmio-muxLars Povlsen1-0/+30
This adds a SPI controller to the Microchip Sparx5 SoC, as well as the mmio-mux that is required to select the right SPI interface for a given SPI device. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-4-lars.povlsen@microchip.com
2020-09-16arm64: dts: sparx5: Add hwmon temperature sensorLars Povlsen1-0/+7
This adds a hwmon temperature node sensor to the Sparx5 SoC. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200618135951.25441-3-lars.povlsen@microchip.com
2020-09-16arm64: dts: sparx5: Add Sparx5 eMMC supportLars Povlsen4-0/+93
This adds eMMC support to the applicable Sparx5 board configuration files. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200825081357.32354-4-lars.povlsen@microchip.com
2020-09-16arm64: dts: qcom: sdm845: Add interconnects property for displayGeorgi Djakov1-0/+4
Add the interconnect paths that are used by the display (MDSS). This will allow the driver to request the needed bandwidth and prevent display flickering. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Link: https://lore.kernel.org/r/20200915214511.786-1-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-16arm64: dts: qcom: sm8250: Add EPSS L3 interconnect providerSibi Sankar1-0/+11
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SM8250 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200801123049.32398-8-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-16arm64: dts: qcom: sm8150: Add OSM L3 interconnect providerSibi Sankar1-0/+11
Add Operation State Manager (OSM) L3 interconnect provider node on SM8150 SoCs. Acked-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200801123049.32398-7-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-16arm64: dts: qcom: sm8250: add interconnect nodesJonathan Marek1-0/+81
Add the interconnect dts nodes for sm8250. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200728023811.5607-8-jonathan@marek.ca Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-16arm64: dts: qcom: sm8150: add interconnect nodesJonathan Marek1-0/+81
Add the interconnect dts nodes for sm8150. Reviewed-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200728023811.5607-7-jonathan@marek.ca Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-16arm64: dts: qcom: sc7180: Increase the number of interconnect cellsSibi Sankar1-109/+109
Increase the number of interconnect-cells, as now we can include the tag information. The consumers can specify the path tag as an additional argument to the endpoints. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Tested-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Link: https://lore.kernel.org/r/20200903133134.17201-8-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-16arm64: dts: qcom: sdm845: Increase the number of interconnect cellsGeorgi Djakov1-24/+24
Increase the number of interconnect-cells, as now we can include the tag information. The consumers can specify the path tag as an additional argument to the endpoints. Tested-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Link: https://lore.kernel.org/r/20200903133134.17201-6-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15KVM: arm64: nVHE: Fix pointers during SMCCC convertionAndrew Scull4-12/+8
The host need not concern itself with the pointer differences for the hyp interfaces that are shared between VHE and nVHE so leave it to the hyp to handle. As the SMCCC function IDs are converted into function calls, it is a suitable place to also convert any pointer arguments into hyp pointers. This, additionally, eases the reuse of the handlers in different contexts. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-20-ascull@google.com
2020-09-15KVM: arm64: nVHE: Migrate hyp-init to SMCCCAndrew Scull5-57/+43
To complete the transition to SMCCC, the hyp initialization is given a function ID. This looks neater than comparing the hyp stub function IDs to the page table physical address. Some care is taken to only clobber x0-3 before the host context is saved as only those registers can be clobbered accoring to SMCCC. Fortunately, only a few acrobatics are needed. The possible new tpidr_el2 is moved to the argument in x2 so that it can be stashed in tpidr_el2 early to free up a scratch register. The page table configuration then makes use of x0-2. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-19-ascull@google.com
2020-09-15KVM: arm64: nVHE: Migrate hyp interface to SMCCCAndrew Scull5-43/+139
Rather than passing arbitrary function pointers to run at hyp, define and equivalent set of SMCCC functions. Since the SMCCC functions are strongly tied to the original function prototypes, it is not expected for the host to ever call an invalid ID but a warning is raised if this does ever occur. As __kvm_vcpu_run is used for every switch between the host and a guest, it is explicitly singled out to be identified before the other function IDs to improve the performance of the hot path. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-18-ascull@google.com
2020-09-15KVM: arm64: nVHE: Pass pointers consistently to hyp-initAndrew Scull2-1/+1
Rather than some being kernel pointer and others being hyp pointers, standardize on all pointers being hyp pointers. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-15-ascull@google.com
2020-09-15KVM: arm64: nVHE: Handle hyp panicsAndrew Scull3-34/+64
Restore the host context when panicking from hyp to give the best chance of the panic being clean. The host requires that registers be preserved such as x18 for the shadow callstack. If the panic is caused by an exception from EL1, the host context is still valid so the panic can return straight back to the host. If the panic comes from EL2 then it's most likely that the hyp context is active and the host context needs to be restored. There are windows before and after the host context is saved and restored that restoration is attempted incorrectly and the panic won't be clean. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-14-ascull@google.com
2020-09-15KVM: arm64: nVHE: Switch to hyp context for EL2Andrew Scull4-19/+89
Save and restore the host context when switching to and from hyp. This gives hyp its own context that the host will not see as a step towards a full trust boundary between the two. SP_EL0 and pointer authentication keys are currently shared between the host and hyp so don't need to be switched yet. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-13-ascull@google.com
2020-09-15KVM: arm64: Share context save and restore macrosAndrew Scull2-39/+39
To avoid duplicating the context save and restore macros, move them into a shareable header. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-12-ascull@google.com
2020-09-15KVM: arm64: Restore hyp when panicking in guest contextAndrew Scull5-4/+44
If the guest context is loaded when a panic is triggered, restore the hyp context so e.g. the shadow call stack works when hyp_panic() is called and SP_EL0 is valid when the host's panic() is called. Use the hyp context's __hyp_running_vcpu field to track when hyp transitions to and from the guest vcpu so the exception handlers know whether the context needs to be restored. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-11-ascull@google.com
2020-09-15KVM: arm64: Update context references from host to hypAndrew Scull2-14/+14
Hyp now has its own nominal context for saving and restoring its state when switching to and from a guest. Update the related comments and utilities to match the new name. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-10-ascull@google.com
2020-09-15KVM: arm64: Introduce hyp contextAndrew Scull7-9/+21
During __guest_enter, save and restore from a new hyp context rather than the host context. This is preparation for separation of the hyp and host context in nVHE. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-9-ascull@google.com
2020-09-15KVM: arm64: nVHE: Don't consume host SErrors with ESBAndrew Scull1-1/+5
The ESB at the start of the host vector may cause SErrors to be consumed to DISR_EL1. However, this is not checked for the host so the SError could go unhandled. Remove the ESB so that SErrors are not consumed but are instead left pending for the host to consume. __guest_enter already defers entry into a guest if there are any SErrors pending. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: James Morse <james.morse@arm.com> Link: https://lore.kernel.org/r/20200915104643.2543892-8-ascull@google.com
2020-09-15KVM: arm64: nVHE: Use separate vector for the hostAndrew Scull7-68/+125
The host is treated differently from the guests when an exception is taken so introduce a separate vector that is specialized for the host. This also allows the nVHE specific code to move out of hyp-entry.S and into nvhe/host.S. The host is only expected to make HVC calls and anything else is considered invalid and results in a panic. Hyp initialization is now passed the vector that is used for the host and it is swapped for the guest vector during the context switch. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-7-ascull@google.com
2020-09-15KVM: arm64: Save chosen hyp vector to a percpu variableAndrew Scull3-2/+7
Introduce a percpu variable to hold the address of the selected hyp vector that will be used with guests. This avoids the selection process each time a guest is being entered and can be used by nVHE when a separate vector is introduced for the host. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-6-ascull@google.com
2020-09-15KVM: arm64: Choose hyp symbol based on contextAndrew Scull1-6/+19
Make CHOOSE_HYP_SYM select the symbol of the active hypervisor for the host, the nVHE symbol for nVHE and the VHE symbol for VHE. The nVHE and VHE hypervisors see their own symbols without prefixes and trigger a link error when trying to use a symbol of the other hypervisor. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: David Brazdil <dbrazdil@google.com> Link: https://lore.kernel.org/r/20200915104643.2543892-5-ascull@google.com
2020-09-15KVM: arm64: Remove kvm_host_data_t typedefAndrew Scull2-5/+3
The kvm_host_data_t typedef is used inconsistently and goes against the kernel's coding style. Remove it in favour of the full struct specifier. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-4-ascull@google.com
2020-09-15KVM: arm64: Remove hyp_panic argumentsAndrew Scull5-16/+15
hyp_panic is able to find all the context it needs from within itself so remove the argument. The __hyp_panic wrapper becomes redundant so is also removed. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-3-ascull@google.com
2020-09-15KVM: arm64: Remove __activate_vm wrapperAndrew Scull3-14/+9
The __activate_vm wrapper serves no useful function and has a misleading name as it simply calls __load_guest_stage2 and does not touch HCR_EL2.VM so remove it. Also rename __deactivate_vm to __load_host_stage2 to match naming pattern. Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200915104643.2543892-2-ascull@google.com
2020-09-15arm64: dts: qcom: Makefile: Sort linesStephan Gerhold1-5/+5
The Makefile is in a bit of a weird order at the moment. It's almost sorted alphabetically, but not entirely. Also, one element uses a space before the += instead of a tab. Fix this up and sort the lines alphabetically so we have a consistent order in the Makefile. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-15-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: pm8916: Sort nodesStephan Gerhold1-30/+30
Sort nodes by unit address so we have a consistent order in pm8916.dtsi. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-14-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: msm8916: Sort nodesStephan Gerhold1-1107/+1107
Just like in commit 50aa72ccb30b ("arm64: dts: qcom: msm8996: Sort all nodes in msm8996.dtsi"), sort all the nodes by unit address, then alphabetically by their name. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-13-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: msm8916: Pad addressesStephan Gerhold1-69/+69
Just like in commit 86f6d6225e5e ("arm64: dts: qcom: msm8996: Pad addresses"), pad all addresses to 8 digits to make it easier to see the correct order of the nodes. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-12-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: msm8916: Rename "x-smp2p" to "smp2p-x"Stephan Gerhold1-2/+2
This allows grouping them together when sorting nodes alphabetically. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-11-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: msm8916: Use more generic node namesStephan Gerhold3-17/+17
Now that all MSM8916 boards are referencing nodes by label instead of name, we can easily make some more nodes use more generic names (as recommended in the device tree specification or the binding documentation). Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-10-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: msm8916: Add MSM8916-specific compatibles to SCM/MSSStephan Gerhold1-2/+2
Over the time, the SCM and MSS driver were refactored to use SoC-specific compatibles. While the generic compatibles still work correctly, add the MSM8916-specific compatibles so they are actually used somewhere. For SCM this will ensure that we actually manage to obtain all three of the specified clocks, since those are required on MSM8916. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-9-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: msm8916: Minor style fixesStephan Gerhold1-13/+13
Fix usages of spaces for indentation, break a long line and remove duplicate new lines. Add some spaces where appropriate. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-8-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: msm8916: Drop qcom,tcsr-mutex sysconStephan Gerhold1-8/+3
The hwlock device node does not (directly) use memory resources of the SoC, so we should move it outside the "soc" node. However, as of commit 7a1e6fb1c606 ("hwspinlock: qcom: Allow mmio usage in addition to syscon") we can now assign the memory region directly to the hwlock device node. This works because the register space used by it is actually separate and not used by any other components. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-7-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: msm8916: Use IRQ defines, add IRQ typesStephan Gerhold1-18/+20
dt-bindings/interrupt-controller/arm-gic.h has a GIC_SPI define that allows specifying interrupts more clearly, but right now only some device nodes in msm8916.dtsi make use of it. Convert all others to use it. The same applies to the IRQ_TYPE_* defines in dt-bindings/interrupt-controller/irq.h. Some interrupts were defined with raw numbers, or even with IRQ_TYPE_NONE (0). Convert all these to use appropriate IRQ types. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-6-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: msm8916: Fix MDP/DSI interruptsStephan Gerhold1-2/+2
The mdss node sets #interrupt-cells = <1>, so its interrupts should be referenced using a single cell (in this case: only the interrupt number). However, right now the mdp/dsi node both have two interrupt cells set, e.g. interrupts = <4 0>. The 0 is probably meant to say IRQ_TYPE_NONE (= 0), but with #interrupt-cells = <1> this is actually interpreted as a second interrupt line. Remove the IRQ flags from both interrupts to fix this. Fixes: 305410ffd1b2 ("arm64: dts: msm8916: Add display support") Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-5-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: pm8916: Remove invalid reg size from wcd_codecStephan Gerhold1-1/+1
Tha parent node of "wcd_codec" specifies #address-cells = <1> and #size-cells = <0>, which means that each resource should be described by one cell for the address and size omitted. However, wcd_codec currently lists 0x200 as second cell (probably the size of the resource). When parsing this would be treated like another memory resource - which is entirely wrong. To quote the device tree specification [1]: "If the parent node specifies a value of 0 for #size-cells, the length field in the value of reg shall be omitted." [1]: https://www.devicetree.org/specifications/ Fixes: 5582fcb3829f ("arm64: dts: apq8016-sbc: add analog audio support with multicodec") Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-4-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: msm8916: Remove one more thermal trip point unit nameStephan Gerhold1-3/+3
Commit fe2aff0c574d2 ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points") removed the unit names for most of the thermal trip points defined in msm8916.dtsi, but missed to update the one for cpu0_1-thermal. So why wasn't this spotted by "make dtbs_check"? Apparently, the name of the thermal zone is already invalid: thermal-zones.yaml specifies a regex of ^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$, so it is not allowed to contain underscores. Therefore the thermal zone was never verified using the DTB schema. After replacing the underscore in the thermal zone name, the warning shows up: apq8016-sbc.dt.yaml: thermal-zones: cpu0-1-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' Fix up the thermal zone names and remove the unit name for the trip point. Cc: Amit Kucheria <amit.kucheria@linaro.org> Fixes: fe2aff0c574d2 ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points") Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-3-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: msm8916: Configure DSI port with labelsStephan Gerhold2-17/+7
&dsi0 -> ports -> port@1 -> endpoint already has the "dsi0_out" label, so we can use it for configuring instead of replicating the entire node hierarchy. Looks like I missed that when converting the boards. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200915071221.72895-2-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: sm8250: Add OPP table for all qup devicesDmitry Baryshkov1-0/+69
qup has a requirement to vote on the performance state of the CX domain in sm8250 devices. Add OPP tables for these and also add power-domains property for all qup instances for uart and spi. i2c does not support scaling and uses a fixed clock. Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200915120203.290295-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: qcom: msm8996: Add VFE1_GDSC power domain to camss nodeRobert Foss1-1/+2
As the MSM8996 has two VFE IP-blocks, and each has a power domain, both of them have to be enabled. Previously only the power domain of VFE0 was enabled, but not the domain for VFE1. This patch adds the VFE1_GDSC power domain to the camss device tree node of the MSM8996 soc. Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://lore.kernel.org/r/20200915142316.147208-1-robert.foss@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15arm64: dts: renesas: r8a77990: Add DRIF supportFabrizio Castro1-0/+120
Add the DRIF controller nodes for the r8a77990 (a.k.a. R-Car E3). Please note that R-Car E3 has register BITCTR located at offset 0x80 (this register is not available on the r8a77960 and r8a77951, whose support has already been upstreamed), and even though it is not dealt with just yet within the driver, we have to keep that into account with our device tree nodes. Also, please note that while testing it has emerged that the HW User Manual has the wrong DMA details for DRIF2 and DRIF3 on E3, as they are only allowed SYS-DMAC0 rather than SYS-DMAC1 and SYS-DMAC2. An errata addressing this issue will be available soon. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Link: https://lore.kernel.org/r/20200911121259.5669-1-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-15arm64: dts: renesas: Drop superfluous pin configuration containersGeert Uytterhoeven2-8/+4
As the pin configuration child nodes for EtherAVB on the Draak and Ebisu boards contain only a single configuration, there is no need to wrap them in additional grandchild containers. Hence remove the superfluous level. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200819123910.19606-1-geert+renesas@glider.be
2020-09-15arm64: dts: qcom: msm8916: Move common USB properties to msm8916.dtsiStephan Gerhold4-11/+3
Right now we define "hnp-disable", "srp-disable", "adp-disable" separately for every MSM8916 board that has USB working. They are needed for USB to work properly if CONFIG_USB_OTG_FSM is enabled. This is because the chipidea OTG FSM code waits for interrupts regarding the VBUS state (AVVIS). Those never happen on MSM8916 because VBUS is always connected to the PMIC instead of the USB controller. There was a patch [1] to work around this but ultimately it was decided that it's easier to disable the OTG FSM altogether using these properties. This works fine for most use cases, because the OTG FSM isn't needed for simple dual role host/gadget operation. Given that these properties are needed for every MSM8916 device, move them to msm8916.dtsi so we can avoid some more duplication. [1]: https://lore.kernel.org/lkml/20160707222114.1673-10-stephen.boyd@linaro.org/ Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200720085406.6716-11-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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