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2021-08-14arm64: dts: imx8mq-reform2: add sound supportLucas Stach1-0/+49
This adds sound support to the Reform2. It differs from the downstream implementation in that the codec is used as the BCLK and FSYNC master and the i.MX8MQ only supplies a fixed 25MHz MCLK from the oscillator. This allows to support a wider range of audio rates by using the codec PLL and to shut down the audio PLLs on the i.MX8MQ SoC side. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8m: drop interrupt-affinity for pmuPeng Fan4-4/+0
i.MX8M use PPI for pmu, interrupt-affinity is not needed. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8qxp: update pmu compatiblePeng Fan1-1/+1
i.MX8QXP features four Cortex-A35 cores, use more accurate compatible. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm: update pmu compatiblePeng Fan1-1/+1
i.MX8MM features four Cortex-A53 cores, update the compatible to use more accurate "arm,cortex-a53-pmu" Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: ls1046a: fix eeprom entriesRaag Jadav2-13/+2
ls1046afrwy and ls1046ardb boards have CAT24C04[1] and CAT24C05[2] eeproms respectively. Both are 4Kb (512 bytes) in size, and compatible with AT24C04[3]. Remove multi-address entries, as both the boards have a single chip each. [1] https://www.onsemi.com/pdf/datasheet/cat24c01-d.pdf [2] https://www.onsemi.com/pdf/datasheet/cat24c03-d.pdf [3] https://ww1.microchip.com/downloads/en/DeviceDoc/doc0180.pdf Signed-off-by: Raag Jadav <raagjadav@gmail.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm-venice-gw7901: enable pull-down on gpio outputsTim Harvey1-3/+3
Enable internal pull-down on UART transceiver GPIO config pins. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm-venice-gw7901: add support for USB hub subloadTim Harvey1-3/+4
The USB hub has it's reset as GPIO4_IO17 but can be sub-loaded and VBUS provided by a VBUS regulator with GPIO4_IO2 as the enable and GPIO1_IO15 as the active-low over-current. Enable pull-up for GPIO4_IO17 to keep hub out of reset and move VBUS enable to GPIO4_IO2. Additionally enable pull-up on GPIO1_IO15 so that if the hub is loaded it never over-currents. This allows USB to work in both configurations without a device-tree change. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm-venice-gw71xx: fix USB OTG VBUSTim Harvey1-2/+3
The GW71xx has a USB Type-C connector with USB 2.0 signaling. GPIO1_12 is the power-enable to the TPS25821 Source controller and power switch responsible for monitoring the CC pins and enabling VBUS. Therefore GPIO1_12 must always be enabled and the vbus output enable from the IMX8MM can be ignored. To fix USB OTG VBUS enable a pull-up on GPIO1_12 to always power the TPS25821 and change the regulator output to GPIO1_10 which is unconnected. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm-venice-gw700x: fix invalid pmic pin configTim Harvey1-8/+0
The GW700x PMIC does not have an interrupt. Remove the invalid pin config. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm-venice-gw700x: fix mp5416 pmic configTim Harvey1-19/+37
Fix various MP5416 PMIC configurations: - Update regulator names per dt-bindings - ensure values fit among valid register values - add required regulator-max-microamp property - add regulator-always-on prop Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mq: add mipi csi phy and csi bridge descriptionsMartin Kepplinger1-0/+104
Describe the 2 available CSI interfaces on the i.MX8MQ with the MIPI-CSI2 receiver (new driver) and the CSI Bridge that provides the user buffers (existing driver). An image sensor is to be connected to the MIPIs' second port, to be described in board files. Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx: Add i.mx8mm/imx8mn Gateworks gw7902 dts supportTim Harvey3-0/+1797
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring: - LPDDR4 DRAM - eMMC FLASH - Gateworks System Controller - LTE CAT M1 modem - USB 2.0 HUB - M.2 Socket with USB2.0, PCIe, and dual-SIM - IMX8M FEC - PCIe based GbE - RS232/RS485/RS422 serial transceiver - GPS - CAN bus - WiFi / Bluetooth - MIPI header (DSI/CSI/GPIO/PWM/I2S) - PMIC Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mp: Add dsp nodeDaniel Baluta1-0/+30
i.MX8 MPlus SoC integrates Cadence HIFI4 DSP. This core runs either a custom firmware or the open source SOF firmware [1] DSP device is handled by SOF OF driver found in sound/soc/sof/sof-of-dev.c Notice that the DSP node makes use of: - dsp_reserved, a reserved memory region for various Audio resources (e.g firmware loading, audio buffers, etc). - Messaging Unit (mu2) for passing notifications betweem ARM core and DSP. [1] https://thesofproject.github.io/latest/platforms/index.html Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8m: Replace deprecated fsl,usbphy DT props with physMarek Vasut2-3/+6
The fsl,usbphy DT property is deprecated, replace it with phys DT property and specify #phy-cells. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mq-evk: Remove unnecessary blank linesKwon Tae-young1-2/+0
Unnecessary blank lines do NOT help readability, so remove them. Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mq-evk: add CD pinctrl for usdhc2Kwon Tae-young1-3/+9
Add CD pinctrl for usdhc2. Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8mm-venice-gw7901: Remove unnecessary #address-cells/#size-cellsFabio Estevam1-2/+0
The following dtc build warning is seen with W=1: arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts:291.14-397.4: Warning (avoid_unnecessary_addr_size): /soc@0/bus@30800000/i2c@30a20000/gsc@20: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Remove the unnecessary #address-cells/#size-cells to fix it. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-By: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8: Add jpeg encoder/decoder nodesMirela Rabulea5-0/+109
Add dts for imaging subsytem, include jpeg nodes here. Tested on imx8qxp/qm. Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: imx8qxp-ai_ml: Fix checkpatch warningsKwon Tae-young1-1/+1
Fix the following warnings reported by checkpatch: arch/..../imx8qxp-ai_ml.dts:198: WARNING: please, no space before tabs Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: ls1088ardb: update PHY nodes with IRQ informationIoana Ciornei1-0/+9
Describe the IRQs for both the QSGMII PHYs and the 10GBASE-R PHY found on the LS1088ARDB board. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: ls2088ardb: update PHY nodes with IRQ informationIoana Ciornei1-0/+4
Update the DTS nodes corresponding to the 4 10GBASE-R PHYs to describe their IRQ lines. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-14arm64: dts: lx2160ardb: update PHY nodes with IRQ informationIoana Ciornei1-0/+4
Update the DTS nodes for both the AR8035 and the AQR107 PHYs in order to describe their IRQ lines. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-08-13arm64: tegra: Fix compatible string for Tegra132 CPUsThierry Reding1-2/+2
The documented compatible string for the CPUs found on Tegra132 is "nvidia,tegra132-denver", rather than the previously used compatible string "nvidia,denver". Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski14-40/+110
Conflicts: drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h 9e26680733d5 ("bnxt_en: Update firmware call to retrieve TX PTP timestamp") 9e518f25802c ("bnxt_en: 1PPS functions to configure TSIO pins") 099fdeda659d ("bnxt_en: Event handler for PPS events") kernel/bpf/helpers.c include/linux/bpf-cgroup.h a2baf4e8bb0f ("bpf: Fix potentially incorrect results with bpf_get_local_storage()") c7603cfa04e7 ("bpf: Add ambient BPF runtime context stored in current") drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c 5957cc557dc5 ("net/mlx5: Set all field of mlx5_irq before inserting it to the xarray") 2d0b41a37679 ("net/mlx5: Refcount mlx5_irq with integer") MAINTAINERS 7b637cd52f02 ("MAINTAINERS: fix Microchip CAN BUS Analyzer Tool entry typo") 7d901a1e878a ("net: phy: add Maxlinear GPY115/21x/24x driver") Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-08-13arm64: dts: HiSilicon: hi3660: address a PCI warningMauro Carvalho Chehab1-1/+1
When the driver is registered, it produces a warning when registering the PCI bridge: [ 5.363450] pci_bus 0000:00: root bus resource [bus 00-01] [ 5.396998] pci_bus 0000:01: busn_res: can not insert [bus 01-ff] under [bus 00-01] (conflicts with (null) [bus 00-01]) [ 5.284831] pci 0000:00:00.0: PCI bridge to [bus 01-ff] The reason is that the bus-range is wrong. Address it. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-08-13Merge tag 'kvmarm-fixes-5.14-2' of ↵Paolo Bonzini2-5/+9
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64 fixes for 5.14, take #2 - Plug race between enabling MTE and creating vcpus - Fix off-by-one bug when checking whether an address range is RAM
2021-08-12Merge tag 'samsung-dt64-5.15' of ↵Arnd Bergmann2-1/+138
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM64 changes for v5.15 1. Add CPU topology and cache information to Exynos DTSI files. 2. Correct GIC CPU interfaces address range on Exynos7. * tag 'samsung-dt64-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7 arm64: dts: exynos: add CPU topology to Exynos5433 arm64: dts: exynos: Add cpu cache information to Exynos5433 arm64: dts: exynos: Add cpu cache information to Exynos7 Link: https://lore.kernel.org/r/20210811085128.30103-2-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-12Merge tag 'amlogic-arm64-dt-for-v5.15' of ↵Arnd Bergmann3-2/+16
git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/dt Amlogic ARM64 DT changes for v5.15: - nanoki-k2: enable bluetooth - khadas vim & vim2: improve wifi * tag 'amlogic-arm64-dt-for-v5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux: arm64: dts: meson: improve gxm-khadas-vim2 wifi arm64: dts: meson: improve gxl-s905x-khadas-vim wifi arm64: dts: meson-gxbb: nanopi-k2: Enable Bluetooth Link: https://lore.kernel.org/r/032895d9-62b6-6c9e-b04b-9c3d316f27ec@baylibre.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-12Merge tag 'ti-k3-dt-for-v5.15' of ↵Arnd Bergmann3-0/+234
git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt Devicetree changes for TI K3 platforms for v5.15 merge window: * New features: - AM64 adds pwm and ecap capability * tag 'ti-k3-dt-for-v5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: arm64: dts: ti: k3-am642-sk: Add pwm nodes arm64: dts: ti: k3-am642-evm: Add pwm nodes arm64: dts: ti: k3-am64-main: Add ecap pwm nodes arm64: dts: ti: k3-am64-main: Add epwm nodes Link: https://lore.kernel.org/r/20210809130631.pfvntcichsyeekbo@festive Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-12Merge tag 'v5.14-next-dts64' of ↵Arnd Bergmann5-1/+19
git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt MT8173: - Add regulator for MFG_ASYNC power domain - Use alias for MMC to get fixed numbers MT8183: - Use alia for MMC to get fixed numbers - Add optional event number for Global Comman Engine * tag 'v5.14-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: dt-bindings: mediatek: Add optional mediatek,gce-events property arm64: dts: mt8183: add mediatek,gce-events in mutex arm64: dts: mediatek: mt8173: Add domain supply for mfg_async arm64: dts: mt8173: elm: Use aliases to mmc nodes arm64: dts: mt8183: kukui: Use aliases to mmc nodes Link: https://lore.kernel.org/r/26c4026a-9f26-d5a3-c30f-439120a4eaa0@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-12arm64: tegra: Add missing interconnects property for USB on Tegra186Thierry Reding1-0/+3
The device tree node for the XUDC (USB device mode controller) is missing the interconnects property that describes the path to memory for the controller. Add the property so that the things like the DMA mask can be set by the operating system. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-12arm64: tegra: Add NVIDIA Jetson TX2 NX Developer Kit supportThierry Reding2-0/+719
The Jetson TX2 NX Developer Kit is very similar to the Jetson Nano, but uses the more powerful Tegra186 SoC. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-12arm64: tegra: Add PWM nodes on Tegra186Thierry Reding1-0/+88
These PWMs can be used for fan or LED backlight control. Add the device tree nodes for all existing controllers found on Tegra186 SoCs. None of these are enabled by default, which is left for the board DTS files to do when necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-12arm64: dts: renesas: r9a07g044: Add I2C interrupt-namesGeert Uytterhoeven1-0/+8
Add "interrupt-names" properties to the I2C device nodes, to make it easier to review the interrupt mappings. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/d35ba11bd705e3c728f94ff0414ac6ae1156244f.1626267422.git.geert+renesas@glider.be
2021-08-11KVM: arm64: Return -EPERM from __pkvm_host_share_hyp()Quentin Perret1-1/+1
Fix the error code returned by __pkvm_host_share_hyp() when the host attempts to share with EL2 a page that has already been shared with another entity. Reported-by: Will Deacon <will@kernel.org> Signed-off-by: Quentin Perret <qperret@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210811173630.2536721-1-qperret@google.com
2021-08-11KVM: arm64: Restrict IPA size to maximum 48 bits on 4K and 16K page sizeAnshuman Khandual1-0/+8
Even though ID_AA64MMFR0.PARANGE reports 52 bit PA size support, it cannot be enabled as guest IPA size on 4K or 16K page size configurations. Hence kvm_ipa_limit must be restricted to 48 bits. This change achieves required IPA capping. Before the commit c9b69a0cf0b4 ("KVM: arm64: Don't constrain maximum IPA size based on host configuration"), the problem here would have been just latent via PHYS_MASK_SHIFT (which earlier in turn capped kvm_ipa_limit), which remains capped at 48 bits on 4K and 16K configs. Cc: Marc Zyngier <maz@kernel.org> Cc: James Morse <james.morse@arm.com> Cc: Alexandru Elisei <alexandru.elisei@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.cs.columbia.edu Cc: linux-kernel@vger.kernel.org Fixes: c9b69a0cf0b4 ("KVM: arm64: Don't constrain maximum IPA size based on host configuration") Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1628680275-16578-1-git-send-email-anshuman.khandual@arm.com
2021-08-11arm64/mm: Define ID_AA64MMFR0_TGRAN_2_SHIFTAnshuman Khandual2-15/+5
Streamline the Stage-2 TGRAN value extraction from ID_AA64MMFR0 register by adding a page size agnostic ID_AA64MMFR0_TGRAN_2_SHIFT. This is similar to the existing Stage-1 TGRAN shift i.e ID_AA64MMFR0_TGRAN_SHIFT. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.cs.columbia.edu Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1628569782-30213-1-git-send-email-anshuman.khandual@arm.com
2021-08-11KVM: arm64: perf: Replace '0xf' instances with ID_AA64DFR0_PMUVER_IMP_DEFAnshuman Khandual2-4/+4
ID_AA64DFR0_PMUVER_IMP_DEF which indicate implementation defined PMU, never actually gets used although there are '0xf' instances scattered all around. Just do the macro replacement to improve readability. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Marc Zyngier <maz@kernel.org> Cc: linux-perf-users@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.cs.columbia.edu Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-08-11KVM: arm64: Make __pkvm_create_mappings staticQuentin Perret2-4/+2
The __pkvm_create_mappings() function is no longer used outside of nvhe/mm.c, make it static. Signed-off-by: Quentin Perret <qperret@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210809152448.1810400-22-qperret@google.com
2021-08-11KVM: arm64: Restrict EL2 stage-1 changes in protected modeQuentin Perret5-12/+118
The host kernel is currently able to change EL2 stage-1 mappings without restrictions thanks to the __pkvm_create_mappings() hypercall. But in a world where the host is no longer part of the TCB, this clearly poses a problem. To fix this, introduce a new hypercall to allow the host to share a physical memory page with the hypervisor, and remove the __pkvm_create_mappings() variant. The new hypercall implements ownership and permission checks before allowing the sharing operation, and it annotates the shared page in the hypervisor stage-1 and host stage-2 page-tables. Signed-off-by: Quentin Perret <qperret@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210809152448.1810400-21-qperret@google.com
2021-08-11KVM: arm64: Refactor protected nVHE stage-1 lockingQuentin Perret2-2/+17
Refactor the hypervisor stage-1 locking in nVHE protected mode to expose a new pkvm_create_mappings_locked() function. This will be used in later patches to allow walking and changing the hypervisor stage-1 without releasing the lock. Signed-off-by: Quentin Perret <qperret@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210809152448.1810400-20-qperret@google.com
2021-08-11KVM: arm64: Remove __pkvm_mark_hypQuentin Perret5-77/+1
Now that we mark memory owned by the hypervisor in the host stage-2 during __pkvm_init(), we no longer need to rely on the host to explicitly mark the hyp sections later on. Remove the __pkvm_mark_hyp() hypercall altogether. Signed-off-by: Quentin Perret <qperret@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210809152448.1810400-19-qperret@google.com
2021-08-11KVM: arm64: Mark host bss and rodata section as sharedQuentin Perret1-8/+74
As the hypervisor maps the host's .bss and .rodata sections in its stage-1, make sure to tag them as shared in hyp and host page-tables. But since the hypervisor relies on the presence of these mappings, we cannot let the host in complete control of the memory regions -- it must not unshare or donate them to another entity for example. To prevent this, let's transfer the ownership of those ranges to the hypervisor itself, and share the pages back with the host. Signed-off-by: Quentin Perret <qperret@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210809152448.1810400-18-qperret@google.com
2021-08-11KVM: arm64: Enable retrieving protections attributes of PTEsQuentin Perret2-0/+57
Introduce helper functions in the KVM stage-2 and stage-1 page-table manipulation library allowing to retrieve the enum kvm_pgtable_prot of a PTE. This will be useful to implement custom walkers outside of pgtable.c. Signed-off-by: Quentin Perret <qperret@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210809152448.1810400-17-qperret@google.com
2021-08-11KVM: arm64: Introduce addr_is_memory()Quentin Perret2-0/+8
Introduce a helper usable in nVHE protected mode to check whether a physical address is in a RAM region or not. Signed-off-by: Quentin Perret <qperret@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210809152448.1810400-16-qperret@google.com
2021-08-11KVM: arm64: Expose pkvm_hyp_idQuentin Perret2-1/+3
Allow references to the hypervisor's owner id from outside mem_protect.c. Signed-off-by: Quentin Perret <qperret@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210809152448.1810400-15-qperret@google.com
2021-08-11KVM: arm64: Expose host stage-2 manipulation helpersQuentin Perret2-1/+19
We will need to manipulate the host stage-2 page-table from outside mem_protect.c soon. Introduce two functions allowing this, and make them usable to users of mem_protect.h. Signed-off-by: Quentin Perret <qperret@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210809152448.1810400-14-qperret@google.com
2021-08-11KVM: arm64: Add helpers to tag shared pages in SW bitsQuentin Perret1-0/+26
We will soon start annotating shared pages in page-tables in nVHE protected mode. Define all the states in which a page can be (owned, shared and owned, shared and borrowed), and provide helpers allowing to convert this into SW bits annotations using the matching prot attributes. Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Quentin Perret <qperret@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210809152448.1810400-13-qperret@google.com
2021-08-11KVM: arm64: Allow populating software bitsQuentin Perret2-1/+16
Introduce infrastructure allowing to manipulate software bits in stage-1 and stage-2 page-tables using additional entries in the kvm_pgtable_prot enum. This is heavily inspired by Marc's implementation of a similar feature in the NV patch series, but adapted to allow stage-1 changes as well: https://lore.kernel.org/kvmarm/20210510165920.1913477-56-maz@kernel.org/ Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Quentin Perret <qperret@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210809152448.1810400-12-qperret@google.com
2021-08-11KVM: arm64: Enable forcing page-level stage-2 mappingsQuentin Perret3-35/+94
Much of the stage-2 manipulation logic relies on being able to destroy block mappings if e.g. installing a smaller mapping in the range. The rationale for this behaviour is that stage-2 mappings can always be re-created lazily. However, this gets more complicated when the stage-2 page-table is used to store metadata about the underlying pages. In such cases, destroying a block mapping may lead to losing part of the state, and confuse the user of those metadata (such as the hypervisor in nVHE protected mode). To avoid this, introduce a callback function in the pgtable struct which is called during all map operations to determine whether the mappings can use blocks, or should be forced to page granularity. This is used by the hypervisor when creating the host stage-2 to force page-level mappings when using non-default protection attributes. Signed-off-by: Quentin Perret <qperret@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210809152448.1810400-11-qperret@google.com
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