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2021-02-12Merge tag 'arm64-fixes' of ↵Linus Torvalds2-6/+3
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fix from Catalin Marinas: "Fix PTRACE_PEEKMTETAGS access to an mmapped region before the first write" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: mte: Allow PTRACE_PEEKMTETAGS access to the zero page
2021-02-12Merge tag 'kvmarm-5.12' of ↵Paolo Bonzini41-323/+873
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64 updates for Linux 5.12 - Make the nVHE EL2 object relocatable, resulting in much more maintainable code - Handle concurrent translation faults hitting the same page in a more elegant way - Support for the standard TRNG hypervisor call - A bunch of small PMU/Debug fixes - Allow the disabling of symbol export from assembly code - Simplification of the early init hypercall handling
2021-02-12arm64: mte: Allow PTRACE_PEEKMTETAGS access to the zero pageCatalin Marinas2-6/+3
The ptrace(PTRACE_PEEKMTETAGS) implementation checks whether the user page has valid tags (mapped with PROT_MTE) by testing the PG_mte_tagged page flag. If this bit is cleared, ptrace(PTRACE_PEEKMTETAGS) returns -EIO. A newly created (PROT_MTE) mapping points to the zero page which had its tags zeroed during cpu_enable_mte(). If there were no prior writes to this mapping, ptrace(PTRACE_PEEKMTETAGS) fails with -EIO since the zero page does not have the PG_mte_tagged flag set. Set PG_mte_tagged on the zero page when its tags are cleared during boot. In addition, to avoid ptrace(PTRACE_PEEKMTETAGS) succeeding on !PROT_MTE mappings pointing to the zero page, change the __access_remote_tags() check to (vm_flags & VM_MTE) instead of PG_mte_tagged. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Fixes: 34bfeea4a9e9 ("arm64: mte: Clear the tags when a page is mapped in user-space with PROT_MTE") Cc: <stable@vger.kernel.org> # 5.10.x Cc: Will Deacon <will@kernel.org> Reported-by: Luis Machado <luis.machado@linaro.org> Tested-by: Luis Machado <luis.machado@linaro.org> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Link: https://lore.kernel.org/r/20210210180316.23654-1-catalin.marinas@arm.com
2021-02-12Merge branch 'for-next/vdso' into for-next/coreWill Deacon7-9/+10
vDSO build improvements. * for-next/vdso: arm64: Support running gen_vdso_offsets.sh with BSD userland. arm64: do not descend to vdso directories twice
2021-02-12Merge branch 'for-next/topology' into for-next/coreWill Deacon1-59/+56
Cleanup to the AMU support code and initialisation rework to support cpufreq drivers built as modules. * for-next/topology: arm64: topology: Make AMUs work with modular cpufreq drivers arm64: topology: Reorder init_amu_fie() a bit arm64: topology: Avoid the have_policy check
2021-02-12Merge branch 'for-next/stacktrace' into for-next/coreWill Deacon2-14/+9
Remove synthetic frame record from exception stack when entering from userspace. * for-next/stacktrace: arm64: remove EL0 exception frame record
2021-02-12Merge branch 'for-next/rng' into for-next/coreWill Deacon1-10/+72
Add support for the TRNG firmware call introduced by Arm spec DEN0098. * for-next/rng: arm64: Add support for SMCCC TRNG entropy source firmware: smccc: Introduce SMCCC TRNG framework firmware: smccc: Add SMCCC TRNG function call IDs
2021-02-12Merge branch 'for-next/perf' into for-next/coreWill Deacon2-4/+18
Perf and PMU updates including support for Cortex-A78 and the v8.3 SPE extensions. * for-next/perf: drivers/perf: Replace spin_lock_irqsave to spin_lock dt-bindings: arm: add Cortex-A78 binding arm64: perf: add support for Cortex-A78 arm64: perf: Constify static attribute_group structs drivers/perf: Prevent forced unbinding of ARM_DMC620_PMU drivers perf/arm-cmn: Move IRQs when migrating context perf/arm-cmn: Fix PMU instance naming perf: Constify static struct attribute_group perf: hisi: Constify static struct attribute_group perf/imx_ddr: Constify static struct attribute_group perf: qcom: Constify static struct attribute_group drivers/perf: Add support for ARMv8.3-SPE
2021-02-12Merge branch 'for-next/misc' into for-next/coreWill Deacon14-33/+59
Miscellaneous arm64 changes for 5.12. * for-next/misc: arm64: Make CPU_BIG_ENDIAN depend on ld.bfd or ld.lld 13.0.0+ arm64: vmlinux.ld.S: add assertion for tramp_pg_dir offset arm64: vmlinux.ld.S: add assertion for reserved_pg_dir offset arm64/ptdump:display the Linear Mapping start marker arm64: ptrace: Fix missing return in hw breakpoint code KVM: arm64: Move __hyp_set_vectors out of .hyp.text arm64: Include linux/io.h in mm/mmap.c arm64: cacheflush: Remove stale comment arm64: mm: Remove unused header file arm64/sparsemem: reduce SECTION_SIZE_BITS arm64/mm: Add warning for outside range requests in vmemmap_populate() arm64: Drop workaround for broken 'S' constraint with GCC 4.9
2021-02-12Merge branch 'for-next/kexec' into for-next/coreWill Deacon9-322/+434
Significant steps along the road to leaving the MMU enabled during kexec relocation. * for-next/kexec: arm64: hibernate: add __force attribute to gfp_t casting arm64: kexec: arm64_relocate_new_kernel don't use x0 as temp arm64: kexec: arm64_relocate_new_kernel clean-ups and optimizations arm64: kexec: call kexec_image_info only once arm64: kexec: move relocation function setup arm64: trans_pgd: hibernate: idmap the single page that holds the copy page routines arm64: mm: Always update TCR_EL1 from __cpu_set_tcr_t0sz() arm64: trans_pgd: pass NULL instead of init_mm to *_populate functions arm64: trans_pgd: pass allocator trans_pgd_create_copy arm64: trans_pgd: make trans_pgd_map_page generic arm64: hibernate: move page handling function to new trans_pgd.c arm64: hibernate: variable pudp is used instead of pd4dp arm64: kexec: make dtb_mem always enabled
2021-02-12Merge branch 'for-next/faultaround' into for-next/coreWill Deacon1-1/+11
Initialise prefaulted PTEs as 'old' for arm64 when hardware access-flag updates are supported, which drastically improves vmscan performance. * for-next/faultaround: mm: filemap: Fix microblaze build failure with 'mmu_defconfig' mm/nommu: Fix return type of filemap_map_pages() mm: Mark anonymous struct field of 'struct vm_fault' as 'const' mm: Use static initialisers for immutable fields of 'struct vm_fault' mm: Avoid modifying vmf.address in __collapse_huge_page_swapin() mm: Pass 'address' to map to do_set_pte() and drop FAULT_FLAG_PREFAULT mm: Move immutable fields of 'struct vm_fault' into anonymous struct arm64: mm: Implement arch_wants_old_prefaulted_pte() mm: Allow architectures to request 'old' entries when prefaulting mm: Cleanup faultaround and finish_fault() codepaths
2021-02-12Merge branch 'for-next/errata' into for-next/coreWill Deacon6-67/+55
Rework of the workaround for Cortex-A76 erratum 1463225 to fit in better with the ongoing exception entry cleanups and changes to the detection code for Cortex-A55 erratum 1024718 since it applies to all revisions of the silicon. * for-next/errata: arm64: entry: consolidate Cortex-A76 erratum 1463225 workaround arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
2021-02-12Merge branch 'for-next/crypto' into for-next/coreWill Deacon1-0/+16
Introduce a new macro to allow yielding the vector unit if preemption is required. The initial users of this are being merged via the crypto tree for 5.12. * for-next/crypto: arm64: assembler: add cond_yield macro
2021-02-12Merge branch 'for-next/cpufeature' into for-next/coreWill Deacon20-170/+511
Support for overriding CPU ID register fields on the command-line, which allows us to disable certain features which the kernel would otherwise use unconditionally when detected. * for-next/cpufeature: (22 commits) arm64: cpufeatures: Allow disabling of Pointer Auth from the command-line arm64: Defer enabling pointer authentication on boot core arm64: cpufeatures: Allow disabling of BTI from the command-line arm64: Move "nokaslr" over to the early cpufeature infrastructure KVM: arm64: Document HVC_VHE_RESTART stub hypercall arm64: Make kvm-arm.mode={nvhe, protected} an alias of id_aa64mmfr1.vh=0 arm64: Add an aliasing facility for the idreg override arm64: Honor VHE being disabled from the command-line arm64: Allow ID_AA64MMFR1_EL1.VH to be overridden from the command line arm64: cpufeature: Add an early command-line cpufeature override facility arm64: Extract early FDT mapping from kaslr_early_init() arm64: cpufeature: Use IDreg override in __read_sysreg_by_encoding() arm64: cpufeature: Add global feature override facility arm64: Move SCTLR_EL1 initialisation to EL-agnostic code arm64: Simplify init_el2_state to be non-VHE only arm64: Move VHE-specific SPE setup to mutate_to_vhe() arm64: Drop early setting of MDSCR_EL2.TPMS arm64: Initialise as nVHE before switching to VHE arm64: Provide an 'upgrade to VHE' stub hypercall arm64: Turn the MMU-on sequence into a macro ...
2021-02-12Merge branch 'kvm-arm64/pmu-debug-fixes-5.11' into kvmarm-master/nextMarc Zyngier3-38/+64
Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-02-12Merge branch 'kvm-arm64/rng-5.12' into kvmarm-master/nextMarc Zyngier4-1/+94
Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-02-12Merge branch 'kvm-arm64/hyp-reloc' into kvmarm-master/nextMarc Zyngier20-135/+604
Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-02-12Merge branch 'kvm-arm64/concurrent-translation-fault' into kvmarm-master/nextMarc Zyngier3-41/+60
Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-02-12Merge branch 'kvm-arm64/misc-5.12' into kvmarm-master/nextMarc Zyngier2-13/+6
Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-02-12Merge tag 'kvmarm-fixes-5.11-2' into kvmarm-master/nextMarc Zyngier4-49/+70
KVM/arm64 fixes for 5.11, take #2 - Don't allow tagged pointers to point to memslots - Filter out ARMv8.1+ PMU events on v8.0 hardware - Hide PMU registers from userspace when no PMU is configured - More PMU cleanups - Don't try to handle broken PSCI firmware - More sys_reg() to reg_to_encoding() conversions Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-02-12Merge remote-tracking branch 'regulator/for-5.12' into regulator-nextMark Brown1-1/+8
2021-02-12dts: marvell: add CM3 SRAM memory to cp11x ethernet device treeKonstantin Porotchkin1-1/+1
CM3 SRAM address space will be used for Flow Control configuration. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11kbuild: LD_VERSION redenominationMasahiro Yamada1-1/+1
Commit ccbef1674a15 ("Kbuild, lto: add ld-version and ld-ifversion macros") introduced scripts/ld-version.sh for GCC LTO. At that time, this script handled 5 version fields because GCC LTO needed the downstream binutils. (https://lkml.org/lkml/2014/4/8/272) The code snippet from the submitted patch was as follows: # We need HJ Lu's Linux binutils because mainline binutils does not # support mixing assembler and LTO code in the same ld -r object. # XXX check if the gcc plugin ld is the expected one too # XXX some Fedora binutils should also support it. How to check for that? ifeq ($(call ld-ifversion,-ge,22710001,y),y) ... However, GCC LTO was not merged into the mainline after all. (https://lkml.org/lkml/2014/4/8/272) So, the 4th and 5th fields were never used, and finally removed by commit 0d61ed17dd30 ("ld-version: Drop the 4th and 5th version components"). Since then, the last 4-digits returned by this script is always zeros. Remove the meaningless last 4-digits. This makes the version format consistent with GCC_VERSION, CLANG_VERSION, LLD_VERSION. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Acked-by: Will Deacon <will@kernel.org> Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-02-11locking/arch: Move qrwlock.h include after qspinlock.hWaiman Long1-1/+1
include/asm-generic/qrwlock.h was trying to get arch_spin_is_locked via asm-generic/qspinlock.h. However, this does not work because architectures might be using queued rwlocks but not queued spinlocks (csky), or because they might be defining their own queued_* macros before including asm/qspinlock.h. To fix this, ensure that asm/spinlock.h always includes qrwlock.h after defining arch_spin_is_locked (either directly for csky, or via asm/qspinlock.h for other architectures). The only inclusion elsewhere is in kernel/locking/qrwlock.c. That one is really unnecessary because the file is only compiled in SMP configurations (config QUEUED_RWLOCKS depends on SMP) and in that case linux/spinlock.h already includes asm/qrwlock.h if needed, via asm/spinlock.h. Reported-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Waiman Long <longman@redhat.com> Fixes: 26128cb6c7e6 ("locking/rwlocks: Add contention detection for rwlocks") Tested-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Ben Gardon <bgardon@google.com> [Add arch/sparc and kernel/locking parts per discussion with Waiman. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-11Merge branch 'dt-for-v5.12' of ↵Arnd Bergmann2-0/+15
git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti into arm/dt * 'dt-for-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti: arm: dts: visconti: Add DT support for Toshiba Visconti5 GPIO driver Link: https://lore.kernel.org/r/20210210173210.nnytfyrkkj6ylrtb@toshiba.co.jp Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-11Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netDavid S. Miller15-38/+33
2021-02-10arm: dts: visconti: Add DT support for Toshiba Visconti5 GPIO driverNobuhiro Iwamatsu2-0/+15
Add the GPIO node in Toshiba Visconti5 SoC-specific DT file. And enable the GPIO node in TMPV7708 RM main board's board-specific DT file. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Reviewed-by: Punit Agrawal <punit1.agrawal@toshiba.co.jp> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2021-02-10crypto: arm64/crc-t10dif - move NEON yield to C codeArd Biesheuvel2-38/+35
Instead of yielding from the bowels of the asm routine if a reschedule is needed, divide up the input into 4 KB chunks in the C glue. This simplifies the code substantially, and avoids scheduling out the task with the asm routine on the call stack, which is undesirable from a CFI/instrumentation point of view. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: arm64/aes-ce-mac - simplify NEON yieldArd Biesheuvel2-40/+33
Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: arm64/aes-neonbs - remove NEON yield callsArd Biesheuvel1-6/+2
There is no need for elaborate yield handling in the bit-sliced NEON implementation of AES, given that skciphers are naturally bounded by the size of the chunks returned by the skcipher_walk API. So remove the yield calls from the asm code. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: arm64/sha512-ce - simplify NEON yieldArd Biesheuvel2-48/+34
Instead of calling into kernel_neon_end() and kernel_neon_begin() (and potentially into schedule()) from the assembler code when running in task mode and a reschedule is pending, perform only the preempt count check in assembler, but simply return early in this case, and let the C code deal with the consequences. This reverts commit 6caf7adc5e458f77f550b6c6ca8effa152d61b4a. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: arm64/sha3-ce - simplify NEON yieldArd Biesheuvel2-56/+39
Instead of calling into kernel_neon_end() and kernel_neon_begin() (and potentially into schedule()) from the assembler code when running in task mode and a reschedule is pending, perform only the preempt count check in assembler, but simply return early in this case, and let the C code deal with the consequences. This reverts commit 7edc86cb1c18b4c274672232117586ea2bef1d9a. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: arm64/sha2-ce - simplify NEON yieldArd Biesheuvel2-35/+25
Instead of calling into kernel_neon_end() and kernel_neon_begin() (and potentially into schedule()) from the assembler code when running in task mode and a reschedule is pending, perform only the preempt count check in assembler, but simply return early in this case, and let the C code deal with the consequences. This reverts commit d82f37ab5e2426287013eba38b1212e8b71e5be3. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: arm64/sha1-ce - simplify NEON yieldArd Biesheuvel2-40/+29
Instead of calling into kernel_neon_end() and kernel_neon_begin() (and potentially into schedule()) from the assembler code when running in task mode and a reschedule is pending, perform only the preempt count check in assembler, but simply return early in this case, and let the C code deal with the consequences. This reverts commit 7df8d164753e6e6f229b72767595072bc6a71f48. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10Merge git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux for-next/cryptoHerbert Xu1-0/+16
Pull change from arm64 tree that's needed for crypto arm changes.
2021-02-10Merge tag 'zynqmp-soc-for-v5.12' of https://github.com/Xilinx/linux-xlnx ↵Arnd Bergmann1-0/+1
into arm/defconfig arm64: soc: ZynqMP SoC changes for v5.12 - Enable clock driver for ZynqMP in defconfig * tag 'zynqmp-soc-for-v5.12' of https://github.com/Xilinx/linux-xlnx: arm64: defconfig: enable clock driver for ZynqMP platforms Link: https://lore.kernel.org/r/2b0f6314-13ba-375a-9231-925b0a07be82@monstr.eu Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-10Merge tag 'v5.12-rockchip-dts64-1' of ↵Arnd Bergmann15-246/+685
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt New boards: Radxa Rock Pi E, NanoPi M4B More fixed indices for mmc nodes; removal of obsolete amba bus nodes; nand-flash-controller nodes for px30 and rk3308; rk3399 pcie ranges fix; board-level fixes for Helios64, NanoPi and Rock960; more sound support for rock64 and rockpro64 and cleanups to make dt-bindings happier. * tag 'v5.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (24 commits) arm64: dts: rockchip: more user friendly name of sound nodes arm64: dts: rockchip: rename pinctrl nodename to gmac2io for nanopi-r2s board arm64: dts: rockchip: assign a fixed index to mmc devices on rk3368 boards arm64: dts: rockchip: assign a fixed index to mmc devices on rk3308 boards arm64: dts: rockchip: assign a fixed index to mmc devices on px30 boards arm64: dts: rockchip: cleanup cpu_thermal node of rk3399-rock960.dts arm64: dts: rockchip: Remove bogus "amba" bus nodes arm64: dts: rockchip: Light "sys" LED on NanoPi R2S arm64: dts: rockchip: fix ranges property format for rk3399 pcie node arm64: dts: rockchip: Rely on SoC external pull up on pmic-int-l on Helios64 arm64: dts: rockchip: Add NanoPi M4B board arm64: dts: rockchip: Move ep-gpios property to nanopc-t4 from nanopi4 arm64: dts: rockchip: Add NFC node for PX30 SoC arm64: dts: rockchip: Add NFC node for RK3308 SoC arm64: dts: rockchip: rk3328: Add Radxa ROCK Pi E dt-bindings: arm: rockchip: Add Radxa ROCK Pi E arm64: dts: rockchip: rk3328: Add clock_in_out property to gmac2phy node arm64: dts: rockchip: rename thermal subnodes for rk3399 arm64: dts: rockchip: rename thermal subnodes for rk3368 arm64: dts: rockchip: add SPDIF node for rk3399-rockpro64 ... Link: https://lore.kernel.org/r/12699743.uLZWGnKmhe@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-09Merge tag 'imx-dt64-5.12' of ↵Arnd Bergmann54-274/+4542
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX arm64 device tree update for 5.12: - New board support: Beacon i.MX8M Nano development kit, i.MX8MM Nitrogen, Gateworks i.MX 8M Mini Development Kits, phyBOARD-Pollux-i.MX8MP, Librem5 Evergreen. - Update imx8mm-beacon to drop unused clock-names reference, and add more pinctrl states for USDHC1. - Support soc unique ID read with NVMEM on i.MX8M SoCs. - A series from Biwen Li to add interrupt line for RTC device on Layerscape SoCs. - A couple of patch sets to update imx8mq-librem5 support around regulators, RTC, charger, display, etc. - A series from Joakim Zhang to improve i.MX8M FEC device configuration. - A series from Kuldeep Singh to enable flexcan support for LX2160A and LS1028A. - A series from Lucas Stach to update ZII devices around audio, USB, I2C pin configuration and UCS1002 ALERT. - A series from Michael Walle to update Layerscape device trees to use constants in the clockgen phandle, add sl28 variant 1 and enable SATA. - A few patches from Russell King to improve support for a couple of LX2160A boards. - A series from Shengjiu Wang to add more audio support for imx8mn-evk. - Other small and random updates. * tag 'imx-dt64-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (71 commits) arm64: dts: imx: Add i.mx8mm nitrogen basic dts support arm64: dts: zii-rmb3: enable RMI4 reduced reporting arm64: dts: zii-ultra: only trigger IRQ on falling edge ucs1002 ALERT pin arm64: dts: zii-ultra: limit USB ports to USB2 speed arm64: dts: zii-ultra: fix i2c pin configuration arm64: dts: zii-ultra: add sound support arm64: dts: ls1028a: Enable flexcan support for LS1028A-RDB/QDS arm64: dts: ls1028a: Update flexcan properties arm64: dts: lx2160a: Add flexcan support arm64: dts: fsl-ls1012a-frdm: add spi-uart device arm64: dts: fsl-ls1012a-rdb: add i2c devices arm64: dts: imx8mn-beacon-som: Enable QSPI on SOM arm64: dts: imx8mn: Add fspi node arm64: dts: Add Librem5 Evergreen arm64: dts: imx8mq-librem5: set regulators boot-on arm64: dts: imx8mq-librem5: enable the LCD panel arm64: dts: imx8mq-librem5: Add LCD_1V8 regulator arm64: dts: imx8mq-librem5: Add usb-c chip as supplier for the charger arm64: dts: imx8mq-librem5: Don't mark buck3 as always on arm64: dts: imx8mq-librem5: Mark charger IRQ as High-Z ... Link: https://lore.kernel.org/r/20210204120150.26186-5-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-09Merge tag 'imx-dt-5.12' of ↵Arnd Bergmann3-3/+3
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX device tree change for 5.12: - A series from Oleksij Rempel to add i.MX6 based Plymovent, Protonic and Kverneland boards. - A series from Andreas Kemnade to improve UART support for ebook readers. - A series from Fabio Estevam to update imx6ul-14x14-evk device tree for adding GPIO expander and camera support. - A patch set from Lucas Stach to improve ZII RDU2 support, enabling WDOG, tuning I2C drive-strength, RMI4 and UCS1002 ALERT. - Other small and random updates on various boards. * tag 'imx-dt-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (37 commits) ARM: dts: imx6: RDU2: adjust audio devices nomenclature ARM: dts: imx6: RDU2: only trigger IRQ on falling edge ucs1002 ALERT pin ARM: dts: imx6: RDU2: enable RMI4 reduced reporting ARM: dts: imx6: RDU2: reduce i2c drive-strength ARM: dts: imx6: rdu2: enable WDOG1 ARM: dts: imx6-sr-som: increase at8035 PHY gigabit Tw parameter ARM: dts: imx6: add wakeup support via magic packet firmware: imx: select SOC_BUS to fix firmware build arm64: dts: imx8mp: Correct the gpio ranges of gpio3 ARM: dts: imx6qdl-sr-som: fix some cubox-i platforms ARM: dts: imx: e60k02: add second uart ARM: dts: imx6sl-tolino-shine3: correct console uart pinmux ARM: dts: imx6sl-tolino-shine2hd: add second uart ARM: dts: imx6sl-tolino-shine2hd: correct console uart pinmux ARM: imx: build suspend-imx6.S with arm instruction set ARM: dts: imx7d-flex-concentrator: fix pcf2127 reset ARM: dts: add Kverneland TGO board ARM: dts: add Kverneland UT1, UT1Q and UT1P ARM: dts: imx6ul-14x14-evk: Add camera support ARM: dts: imx6ul-14x14-evk: Describe the KSZ8081 reset ... Link: https://lore.kernel.org/r/20210204120150.26186-4-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-09Merge tag 'qcom-arm64-for-5.12' of ↵Arnd Bergmann53-1328/+6468
git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt Qualcomm ARM64 DT updates for 5.12 This introduces initial support for the new SM8350 platform, aka Snapdragon 888, and the MTP device for this. It adds PCIe, audio, display, GPU, HDMI watchdog, LLCC and PMIC ADC support to the SM8250 platform and RB5 in particular, as well as improve the definition of CPUs, thermal zones and fixes a few smaller issues. It introduces new Devicetree files for the Alcatel Idol 3, ASUS Zenfone 2 Laser and BQ Aquaris X5, based on the MSM8916 platform. It contains an overhaul of the existing MSM8992 and MSM8994 platform files and introduces RPM power domains and SMP2P nodes. It adds touchscreen, additional regulators, microSD card support and adds the Sony Mobile Ivy, Karin, Suzuran and Satsuki devices. It joins the common parts of the Lumia 950 and 950XL and extend these with support for sensors, NFC, bluetooth, audio, microSD and Type-C mux pins. It introduces support for the OnePlus6 and 6t, adds the missing higher frequences for the SDM850 laptops, adds CPU cluster idle support on SM8150 and a few tweaks to the SC7180 platform. * tag 'qcom-arm64-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (100 commits) arm64: dts: qcom: msm8998: Use rpmpd definitions for opp table levels arm64: dts: qcom: msm8996: Add missing device_type under pcie[01] arm64: dts: qcom: sc7180: Add support for gpu fuse arm64: dts: qcom: msm8998: Disable some components by default arm64: dts: qcom: msm8998: Add capacity-dmips-mhz to CPU cores arm64: dts: qcom: msm8998: Add I2C pinctrl and fix BLSP2_I2C naming arm64: dts: qcom: msm8998: Add DMA to I2C hosts arm64: dts: qcom: msm8998: Merge in msm8998-pins.dtsi to msm8998.dtsi arm64: dts: msm8916: Fix reserved and rfsa nodes unit address arm64: dts: qcom: msm8994-octagon: Add AD7147 and APDS9930 sensors arm64: dts: qcom: msm8994-octagon: Add TAS2553 codec arm64: dts: qcom: msm8994-octagon: Add sensors on blsp1_i2c5 arm64: dts: qcom: msm8994-octagon: Add NXP NFC node arm64: dts: qcom: msm8994-octagon: Add FM Radio and DDR regulator nodes arm64: dts: qcom: msm8994-octagon: Configure PON keys arm64: dts: qcom: msm8994-octagon: Configure Lattice iCE40 FPGA arm64: dts: qcom: msm8994-octagon: Add uSD card and disable HS400 on eMMC arm64: dts: qcom: msm8994-octagon: Configure HD3SS460 Type-C mux pins arm64: dts: qcom: msm8994-octagon: Add QCA6174 bluetooth arm64: dts: qcom: msm8994-octagon: Configure regulators ... Link: https://lore.kernel.org/r/20210204052043.388621-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-09Merge tag 'amlogic-dt64-1' of ↵Arnd Bergmann29-478/+731
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: amlogic updates for v5.12 - new board: Hardkernel ODROID-HC4 (SoC: SM1) - new board: Beelink GS-King-X (SoC: S922X) - shorten shorten audio card names for alsa compatibility - misc cleanups & fixes * tag 'amlogic-dt64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson: add initial device-tree for ODROID-HC4 dt-bindings: arm: amlogic: add ODROID-HC4 bindings arm64: dts: meson: convert meson-sm1-odroid-c4 to dtsi arm64: dts: meson: sort Amlogic dtb Makefile dt-bindings: arm: amlogic: sort SM1 bindings arm64: dts: meson: fix broken wifi node for Khadas VIM3L arm64: dts: meson: add i2c3/rtc nodes and rtc aliases to ODROID-N2 dtsi ARM: dts: meson: add the AO ARC remote processor dt-bindings: Amlogic: add the documentation for the SECBUS2 registers dt-bindings: sram: Add compatible strings for the Meson AO ARC SRAM arm64: dts: meson: shorten audio card names for alsa compatibility arm64: dts: meson: add initial Beelink GS-King-X device-tree dt-bindings: arm: amlogic: add support for the Beelink GS-King-X arm64: dts: meson: Fix schema warnings for pwm-leds arm64: dts: meson: vim3: whitespace fixups arm64: dts: meson: switch TFLASH_VDD_EN pin to open drain on Odroid-C4 Revert "arm64: dts: amlogic: add missing ethernet reset ID" arm64: dts: amlogic: meson-g12: Set FL-adj property value Link: https://lore.kernel.org/soc/7heehq7ag3.fsf@baylibre.com/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-09Merge tag 'zynqmp-dt-for-v5.12' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann9-4/+766
arm/dt arm64: dts: ZynqMP DT changes for v5.12 - Wire clock chips present on boards - Enable reset, qspi, nand, watchdog and DP IPs - Enable phy driver for sata and DP - Add iommu description - Add support for zcu104 revC+ boards - Various small changes - Add missing labels - Fix typos in documentation - Add missing boards * tag 'zynqmp-dt-for-v5.12' of https://github.com/Xilinx/linux-xlnx: arm64: dts: zynqmp: Wire up the DisplayPort subsystem arm64: dts: zynqmp: Add DisplayPort subsystem arm64: dts: zynqmp: Add DPDMA node dt-bindings: arm: Fix typo in zcu111 board arm64: dts: zynqmp: Add description for zcu104 revC arm64: dts: zynqmp: Add missing iommu IDs arm64: dts: zynqmp: Add missing lpd watchdog node arm64: dts: zynqmp: Wire zynqmp qspi controller arm64: dts: zynqmp: Wire arasan nand controller arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis arm64: dts: zynqmp: Add label for zynqmp_ipi arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106 arm64: dts: zynqmp: Enable reset controller driver arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111 arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106 arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111 arm64: dts: zynqmp: Add address-cells property to interrupt controllers Link: https://lore.kernel.org/r/b1a6f89e-f6b4-757b-daf0-d2f1844b833d@xilinx.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-09arm64: Make CPU_BIG_ENDIAN depend on ld.bfd or ld.lld 13.0.0+Nathan Chancellor1-2/+3
Similar to commit 28187dc8ebd9 ("ARM: 9025/1: Kconfig: CPU_BIG_ENDIAN depends on !LD_IS_LLD"), ld.lld prior to 13.0.0 does not properly support aarch64 big endian, leading to the following build error when CONFIG_CPU_BIG_ENDIAN is selected: ld.lld: error: unknown emulation: aarch64linuxb This has been resolved in LLVM 13. To avoid errors like this, only allow CONFIG_CPU_BIG_ENDIAN to be selected if using ld.bfd or ld.lld 13.0.0 and newer. While we are here, the indentation of this symbol used spaces since its introduction in commit a872013d6d03 ("arm64: kconfig: allow CPU_BIG_ENDIAN to be selected"). Change it to tabs to be consistent with kernel coding style. Link: https://github.com/ClangBuiltLinux/linux/issues/380 Link: https://github.com/ClangBuiltLinux/linux/issues/1288 Link: https://github.com/llvm/llvm-project/commit/7605a9a009b5fa3bdac07e3131c8d82f6d08feb7 Link: https://github.com/llvm/llvm-project/commit/eea34aae2e74e9b6fbdd5b95f479bc7f397bf387 Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Link: https://lore.kernel.org/r/20210209005719.803608-1-nathan@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2021-02-09arm64: cpufeatures: Allow disabling of Pointer Auth from the command-lineMarc Zyngier3-1/+20
In order to be able to disable Pointer Authentication at runtime, whether it is for testing purposes, or to work around HW issues, let's add support for overriding the ID_AA64ISAR1_EL1.{GPI,GPA,API,APA} fields. This is further mapped on the arm64.nopauth command-line alias. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: David Brazdil <dbrazdil@google.com> Tested-by: Srinivas Ramana <sramana@codeaurora.org> Link: https://lore.kernel.org/r/20210208095732.3267263-23-maz@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2021-02-09arm64: Defer enabling pointer authentication on boot coreSrinivas Ramana3-4/+11
Defer enabling pointer authentication on boot core until after its required to be enabled by cpufeature framework. This will help in controlling the feature dynamically with a boot parameter. Signed-off-by: Ajay Patil <pajay@qti.qualcomm.com> Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org> Signed-off-by: Srinivas Ramana <sramana@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1610152163-16554-2-git-send-email-sramana@codeaurora.org Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: David Brazdil <dbrazdil@google.com> Link: https://lore.kernel.org/r/20210208095732.3267263-22-maz@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2021-02-09arm64: cpufeatures: Allow disabling of BTI from the command-lineMarc Zyngier4-2/+16
In order to be able to disable BTI at runtime, whether it is for testing purposes, or to work around HW issues, let's add support for overriding the ID_AA64PFR1_EL1.BTI field. This is further mapped on the arm64.nobti command-line alias. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: David Brazdil <dbrazdil@google.com> Tested-by: Srinivas Ramana <sramana@codeaurora.org> Link: https://lore.kernel.org/r/20210208095732.3267263-21-maz@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2021-02-09arm64: Move "nokaslr" over to the early cpufeature infrastructureMarc Zyngier2-34/+17
Given that the early cpufeature infrastructure has borrowed quite a lot of code from the kaslr implementation, let's reimplement the matching of the "nokaslr" option with it. Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: David Brazdil <dbrazdil@google.com> Link: https://lore.kernel.org/r/20210208095732.3267263-20-maz@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2021-02-09arm64: Make kvm-arm.mode={nvhe, protected} an alias of id_aa64mmfr1.vh=0Marc Zyngier2-0/+5
Admitedly, passing id_aa64mmfr1.vh=0 on the command-line isn't that easy to understand, and it is likely that users would much prefer write "kvm-arm.mode=nvhe", or "...=protected". So here you go. This has the added advantage that we can now always honor the "kvm-arm.mode=protected" option, even when booting on a VHE system. Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: David Brazdil <dbrazdil@google.com> Link: https://lore.kernel.org/r/20210208095732.3267263-18-maz@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2021-02-09arm64: Add an aliasing facility for the idreg overrideMarc Zyngier1-3/+14
In order to map the override of idregs to options that a user can easily understand, let's introduce yet another option array, which maps an option to the corresponding idreg options. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: David Brazdil <dbrazdil@google.com> Link: https://lore.kernel.org/r/20210208095732.3267263-17-maz@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2021-02-09arm64: Honor VHE being disabled from the command-lineMarc Zyngier2-0/+14
Finally we can check whether VHE is disabled on the command line, and not enable it if that's the user's wish. Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: David Brazdil <dbrazdil@google.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20210208095732.3267263-16-maz@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-23 18:41:40 +0300