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2021-04-08arm64: Disable fine grained traps on bootMark Brown2-0/+27
The arm64 FEAT_FGT extension introduces a set of traps to EL2 for accesses to small sets of registers and instructions from EL1 and EL0. Currently Linux makes no use of this feature, ensure that it is not active at boot by disabling the traps during EL2 setup. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210401180942.35815-3-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2021-04-08arm64: mte: Remove unused mte_assign_mem_tag_range()Vincenzo Frascino1-6/+0
mte_assign_mem_tag_range() was added in commit 85f49cae4dfc ("arm64: mte: add in-kernel MTE helpers") in 5.11 but moved out of mte.S by commit 2cb34276427a ("arm64: kasan: simplify and inline MTE functions") in 5.12 and renamed to mte_set_mem_tag_range(). 2cb34276427a did not delete the old function prototypes in mte.h. Remove the unused prototype from mte.h. Cc: Will Deacon <will@kernel.org> Reported-by: Derrick McKee <derrick.mckee@gmail.com> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Link: https://lore.kernel.org/r/20210407133817.23053-1-vincenzo.frascino@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2021-04-08arm64: Add __init section marker to some functionsJisheng Zhang4-6/+6
They are not needed after booting, so mark them as __init to move them to the .init section. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Reviewed-by: Steven Price <steven.price@arm.com> Link: https://lore.kernel.org/r/20210330135449.4dcffd7f@xhacker.debian Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2021-04-08arm64/sve: Rework SVE access trap to convert state in registersMark Brown3-9/+23
When we enable SVE usage in userspace after taking a SVE access trap we need to ensure that the portions of the register state that are not shared with the FPSIMD registers are zeroed. Currently we do this by forcing the FPSIMD registers to be saved to the task struct and converting them there. This is wasteful in the common case where the task state is loaded into the registers and we will immediately return to userspace since we can initialise the SVE state directly in registers instead of accessing multiple copies of the register state in memory. Instead in that common case do the conversion in the registers and update the task metadata so that we can return to userspace without spilling the register state to memory unless there is some other reason to do so. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20210312190313.24598-1-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2021-04-08Merge tag 'sunxi-fixes-for-5.12-1' of ↵Arnd Bergmann4-7/+7
git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes One 32kHz clock fix for the beelink gs1, a CD polarity fix for the SoPine, some MAINTAINERS maintainance, and a clk / reset switch to our headers. * tag 'sunxi-fixes-for-5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: h6: beelink-gs1: Remove ext. 32 kHz osc reference MAINTAINERS: Match on allwinner keyword MAINTAINERS: Add our new mailing-list arm64: dts: allwinner: Fix SD card CD GPIO for SOPine systems arm64: dts: allwinner: h6: Switch to macros for RSB clock/reset indices Link: https://lore.kernel.org/r/9972a85e-60b7-49f4-a246-db3396dd4764.lettre@localhost Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-08arm64: dts: qcom: update usb qmp phy clock-cells propertyJonathan Marek3-5/+6
The top-level node doesn't provide any clocks, the subnode provides a single clock with of_clk_hw_simple_get. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20201123143705.14277-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-04-08arm64: dts: qcom: msm8916: Add GICv2 hypervisor registers/interruptStephan Gerhold1-1/+3
The ARM Cortex-A53 CPU cores and QGIC2 interrupt controller (an implementation of the ARM GIC 2.0 specification) used in MSM8916 support virtualization, e.g. for KVM on Linux. However, so far it was not possible to make use of this functionality, because Qualcomm's proprietary "hyp" firmware blocks the EL2 mode of the CPU and only allows booting Linux in EL1. However, on devices without (firmware) secure boot there is no need to rely on all of Qualcomm's firmware. The "hyp" firmware on MSM8916 seems simple enough that it can be replaced with an open-source alternative created only based on trial and error - with some similar EL2/EL1 initialization code adapted from Linux and U-Boot. qhypstub [1] is such an open-source firmware for MSM8916 that can be used as drop-in replacement for Qualcomm's "hyp" firmware. It does not implement any hypervisor functionality. Instead, it allows booting Linux/KVM (or other hypervisors) in EL2. With Linux booting in EL2, KVM seems to be working just fine on MSM8916. However, so far it is not possible to make use of the virtualization features in the GICv2. To use KVM's VGICv2 code, the QGIC2 device tree node needs additional resources (according to binding documentation): - The CPU interface region (second reg) must be at least 8 KiB large to access the GICC_DIR register (mapped at 0x1000 offset) - Virtual control/CPU interface register base and size - Hypervisor maintenance interrupt Fortunately, the public APQ8016E TRM [2] provides the required information: - The CPU interface region (at 0x0B002000) actually has a size of 8 KiB - Virtual control/CPU interface register is at 0x0B001000/0x0B004000 - Hypervisor maintenance interrupt is "PPI #0" Note: This is a bit strange since almost all other ARM SoCs use GIC_PPI 9 for this. However, I have verified that this is indeed the interrupt that fires when bits are set in GICH_HCR. Add the additional resources to the QGIC2 device tree node in msm8916.dtsi. There is no functional difference when Linux is started in EL1 since the additional resources are ignored in that case. With these changes (and qhypstub), KVM seems to be fully working on the DragonBoard 410c (apq8016-sbc) and BQ Aquaris X5 (longcheer-l8910). [1]: https://github.com/msm8916-mainline/qhypstub [2]: https://developer.qualcomm.com/download/sd410/snapdragon-410e-technical-reference-manual.pdf Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20210407163648.4708-1-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-04-08arm64: entry: Enable random_kstack_offset supportKees Cook3-0/+22
Allow for a randomized stack offset on a per-syscall basis, with roughly 5 bits of entropy. (And include AAPCS rationale AAPCS thanks to Mark Rutland.) In order to avoid unconditional stack canaries on syscall entry (due to the use of alloca()), also disable stack protector to avoid triggering needless checks and slowing down the entry path. As there is no general way to control stack protector coverage with a function attribute[1], this must be disabled at the compilation unit level. This isn't a problem here, though, since stack protector was not triggered before: examining the resulting syscall.o, there are no changes in canary coverage (none before, none now). [1] a working __attribute__((no_stack_protector)) has been added to GCC and Clang but has not been released in any version yet: https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=346b302d09c1e6db56d9fe69048acb32fbb97845 https://reviews.llvm.org/rG4fbf84c1732fca596ad1d6e96015e19760eb8a9b Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20210401232347.2791257-6-keescook@chromium.org
2021-04-08arm64: apple: Add initial Apple Mac mini (M1, 2020) devicetreeHector Martin4-0/+183
This currently supports: * SMP (via spin-tables) * AIC IRQs * Serial (with earlycon) * Framebuffer A number of properties are dynamic, and based on system firmware decisions that vary from version to version. These are expected to be filled in by the loader. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-04-08arm64: Kconfig: Introduce CONFIG_ARCH_APPLEHector Martin2-0/+8
This adds a Kconfig option to toggle support for Apple ARM SoCs. At this time this targets the M1 and later "Apple Silicon" Mac SoCs. Signed-off-by: Hector Martin <marcan@marcan.st>
2021-04-08arm64: Move ICH_ sysreg bits from arm-gic-v3.h to sysreg.hHector Martin1-0/+60
These definitions are in arm-gic-v3.h for historical reasons which no longer apply. Move them to sysreg.h so the AIC driver can use them, as it needs to peek into vGIC registers to deal with the GIC maintentance interrupt. Acked-by: Marc Zyngier <maz@kernel.org> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-04-08asm-generic/io.h: implement pci_remap_cfgspace using ioremap_npHector Martin1-10/+0
Now that we have ioremap_np(), we can make pci_remap_cfgspace() default to it, falling back to ioremap() on platforms where it is not available. Remove the arm64 implementation, since that is now redundant. Future cleanups should be able to do the same for other arches, and eventually make the generic pci_remap_cfgspace() unconditional. Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-04-08arm64: Implement ioremap_np() to map MMIO as nGnRnEHector Martin1-0/+1
This is used on Apple ARM platforms, which require most MMIO (except PCI devices) to be mapped as nGnRnE. Acked-by: Marc Zyngier <maz@kernel.org> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-04-08arm64: cputype: Add CPU implementor & types for the Apple M1 coresHector Martin1-0/+6
The implementor will be used to condition the FIQ support quirk. The specific CPU types are not used at the moment, but let's add them for documentation purposes. Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-04-07Merge tag 'arm-fixes-5.11-2' of ↵Linus Torvalds3-5/+5
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC fixes from Arnd Bergmann: "Most of the changes again are devicetree fixes, but there are also five trivial build fixes for issues I found when test building with gcc-11 or when running 'make W=1', and some OMAP platform specific code fixups. Broadcom: - One revert for a Raspberry pi interrupt controller change that caused a regression. TI OMAP: - Remove unused duplicate sha2md5_fck clock node that can race with the OMAP4_SHA2MD5_CLKCTRL clock node for disable for unused clocks - Add aliases for omap4/5 mmc to put the slots back into the right order again - Fix typo for bionic voltage controllers that accidentally use mpu for all instances instead of mpu, core and iva - Fix random hangs for droid4 caused by missing fix from TI Android kernel tree to do a dummy smc call on cpuidle wakeup path NXP i.MX: - Fix a system failure on imx6qdl-phytec-pfla02 board when booting from SD, by adding missing vmmc supply for SD interfaces. - Fix address typo in i.MX8MM/Q IOMUXC_SD1_DATA0_GPIO2_IO2 definition. Marvell mvebu: - Fix storm interrupt on Turris Omnia - Enable hardware buffer management as it should be ... and build fixes for PXA, Freescale, Marvell, OMAP1 and Keystone" * tag 'arm-fixes-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: ARM: dts: turris-omnia: configure LED[2]/INTn pin as interrupt pin ARM: dts: turris-omnia: fix hardware buffer management Revert "arm64: dts: marvell: armada-cp110: Switch to per-port SATA interrupts" ARM: mvebu: avoid clang -Wtautological-constant warning ARM: pxa: mainstone: avoid -Woverride-init warning ARM: omap1: fix building with clang IAS soc/fsl: qbman: fix conflicting alignment attributes ARM: keystone: fix integer overflow warning ARM: dts: imx6: pbab01: Set vmmc supply for both SD interfaces arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0 ARM: OMAP4: PM: update ROM return address for OSWR and OFF ARM: OMAP4: Fix PMIC voltage domains for bionic ARM: dts: Fix moving mmc devices with aliases for omap4 & 5 ARM: dts: Drop duplicate sha2md5_fck to fix clk_disable race Revert "ARM: dts: bcm2711: Add the BSC interrupt controller"
2021-04-07arm64: dts: meson: add GPIO line names to ODROID N2/N2+Hyeonki Hong1-0/+45
Add GPIO line-name identifiers to the ODROID N2/N2+ common dtsi. Signed-off-by: Hyeonki Hong <hhk7734@gmail.com> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20210407042609.9736-4-christianshewitt@gmail.com
2021-04-07arm64: dts: meson: add saradc node to ODROID N2/N2+Hyeonki Hong1-0/+5
Add the meson saradc node to the ODROID N2/N2+ common dtsi. Signed-off-by: Hyeonki Hong <hhk7734@gmail.com> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20210407042609.9736-3-christianshewitt@gmail.com
2021-04-07arm64: dts: meson: remove extra tab from ODROID N2/N2+ ext_mdio nodeChristian Hewitt1-1/+1
Remove an extra tab from the ext_mdio node in the ODROID N2/N2+ common dtsi file. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20210407042609.9736-2-christianshewitt@gmail.com
2021-04-07KVM: arm64: Initialize VCPU mdcr_el2 before loading itAlexandru Elisei3-28/+63
When a VCPU is created, the kvm_vcpu struct is initialized to zero in kvm_vm_ioctl_create_vcpu(). On VHE systems, the first time vcpu.arch.mdcr_el2 is loaded on hardware is in vcpu_load(), before it is set to a sensible value in kvm_arm_setup_debug() later in the run loop. The result is that KVM executes for a short time with MDCR_EL2 set to zero. This has several unintended consequences: * Setting MDCR_EL2.HPMN to 0 is constrained unpredictable according to ARM DDI 0487G.a, page D13-3820. The behavior specified by the architecture in this case is for the PE to behave as if MDCR_EL2.HPMN is set to a value less than or equal to PMCR_EL0.N, which means that an unknown number of counters are now disabled by MDCR_EL2.HPME, which is zero. * The host configuration for the other debug features controlled by MDCR_EL2 is temporarily lost. This has been harmless so far, as Linux doesn't use the other fields, but that might change in the future. Let's avoid both issues by initializing the VCPU's mdcr_el2 field in kvm_vcpu_vcpu_first_run_init(), thus making sure that the MDCR_EL2 register has a consistent value after each vcpu_load(). Fixes: d5a21bcc2995 ("KVM: arm64: Move common VHE/non-VHE trap config in separate functions") Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210407144857.199746-3-alexandru.elisei@arm.com
2021-04-07Merge tag 'samsung-dt64-5.13' of ↵Arnd Bergmann2-4/+4
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM64 changes for v5.13 Two cleanups in DTS without expected impact. * tag 'samsung-dt64-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: white-space cleanups arm64: dts: exynos: re-order Slim SSS clocks to match dtschema Link: https://lore.kernel.org/r/20210407065828.7213-2-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-07KVM: arm64: Add support for the KVM PTP serviceJianyong Wu2-0/+54
Implement the hypervisor side of the KVM PTP interface. The service offers wall time and cycle count from host to guest. The caller must specify whether they want the host's view of either the virtual or physical counter. Signed-off-by: Jianyong Wu <jianyong.wu@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20201209060932.212364-7-jianyong.wu@arm.com
2021-04-07Merge tag 'amlogic-dt64' of ↵Arnd Bergmann6-0/+334
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: amlogic updates for v5.13 - new boards: MeCool KII & KIII, Minix NEO U9-H - used fixed index for MMC devices * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson: add initial device-tree for MeCool KIII Pro arm64: dts: meson: add initial device-tree for MeCool KII Pro dt-bindings: arm: amlogic: add MeCool KII/KIII Pro bindings arm64: dts: amlogic: Assign a fixed index to mmc devices arm64: dts: meson: add initial device-tree for Minix NEO U9-H dt-bindings: arm: amlogic: add support for the Minix NEO U9-H Link: https://lore.kernel.org/r/7h5z10mjpp.fsf@baylibre.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-07Merge tag 'ti-k3-dt-for-v5.13' of ↵Arnd Bergmann20-10/+3486
git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt Devicetree changes for TI K3 platforms for v5.13 merge window: * New SoCs: - AM642 mean for industrial control, motor control, remote IO, IoT gateway etc. * New Boards: - AM65: Siemens SIMATIC IOT2050 advanced and basic boards - AM64: EVM and SK boards * New peripherals: - AM65: watchdog - AM65,J721E: ICSSG - J7200: OSPI, GPIO * Fixes: - AM65: pcie node fixup, ospi speed updates - J721e, J7200: MMC speed updates, ospi speed updates and compatibles fixups. * tag 'ti-k3-dt-for-v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: (39 commits) arm64: dts: ti: k3-am64-main: Fix ospi compatible arm64: dts: ti: k3-j7200-mcu: Fix ospi compatible arm64: dts: ti: k3-j721e-mcu: Fix ospi compatible arm64: dts: ti: k3-j7200: Add support for higher speed modes and update delay select values for MMCSD subsystems arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio modules arm64: dts: ti: k3-j7200: Add gpio nodes arm64: dts: ti: k3-am642-evm/sk: Add IPC sub-mailbox nodes arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes arm64: dts: ti: k3-am64-main: Add hwspinlock node arm64: dts: ti: k3-am642: reserve gpio in mcu domain for firmware usage arm64: dts: ti: k3-am64: Add GPIO DT nodes arm64: dts: ti: k3-am64-evm/sk: Add OSPI flash DT node arm64: dts: ti: k3-am64-main: Add OSPI node arm64: dts: ti: k3-am64-main: Add ADC nodes arm64: dts: ti: k3-am642-evm: Add USB support arm64: dts: ti: k3-am64-main: Add DT node for USB subsystem arm64: dts: ti: Add support for Siemens IOT2050 boards dt-bindings: arm: ti: Add bindings for Siemens IOT2050 boards dt-bindings: Add Siemens vendor prefix arm64: dts: ti: k3-am642-evm: Add support for SPI EEPROM ... Link: https://lore.kernel.org/r/20210405155336.smohb7uzkperqwuz@reflex Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-07KVM: arm64: Don't retrieve memory slot again in page fault handlerGavin Shan1-2/+7
We needn't retrieve the memory slot again in user_mem_abort() because the corresponding memory slot has been passed from the caller. This would save some CPU cycles. For example, the time used to write 1GB memory, which is backed by 2MB hugetlb pages and write-protected, is dropped by 6.8% from 928ms to 864ms. Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Keqian Zhu <zhukeqian1@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210316041126.81860-4-gshan@redhat.com
2021-04-07KVM: arm64: Use find_vma_intersection()Gavin Shan1-4/+6
find_vma_intersection() has been existing to search the intersected vma. This uses the function where it's applicable, to simplify the code. Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Keqian Zhu <zhukeqian1@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210316041126.81860-3-gshan@redhat.com
2021-04-07KVM: arm64: Hide kvm_mmu_wp_memory_region()Gavin Shan2-2/+1
We needn't expose the function as it's only used by mmu.c since it was introduced by commit c64735554c0a ("KVM: arm: Add initial dirty page locking support"). Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Keqian Zhu <zhukeqian1@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210316041126.81860-2-gshan@redhat.com
2021-04-07Merge tag 'qcom-arm64-for-5.13' of ↵Arnd Bergmann44-453/+3535
git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt Qualcomm ARM64 DT updates for 5.13 This extends the initial SM8350 description merged in v5.12 with CPUfreq, SMMU, UFS, RPMHPD, SPMI, USB and remoteproc support. It adds initial PMIC definitions for the 6 PMICs found on the MTP and it introduces the new SM8350 Hardware Development Kit (HDK). SC7180 is further polished, the DisplayPort portion of the QMP phy is defined and several new SKUs of the Trogdor devices are introduced. The new SC7280 platform is introduced, with RPMH, RPMHPD, RPMCC, SPMI, CPU idle, SMMU and watchdog defined. SDM845 gains the camera related nodes and some cleanups. For SM8250 it brings some cleanups and migrates SPI0 to use GPIO for chip select. * tag 'qcom-arm64-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (79 commits) arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS arm64: dts: qcom: sm8250: further split of spi pinctrl config arm64: dts: qcom: sm8250: split spi pinctrl config arm64: dts: qcom: sdm845-db845c: Enable ov8856 sensor and connect to ISP arm64: dts: qcom: sdm845-db845c: Configure regulators for camss node arm64: dts: qcom: sdm845: Add CAMSS ISP node arm64: dts: qcom: pm8150: Enable RTC arm64: dts: qcom: sm8350-mtp: Add PMICs arm64: dts: qcom: pmr735B: Add base dts file arm64: dts: qcom: pmr735a: Add base dts file arm64: dts: qcom: pm8350c: Add base dts file arm64: dts: qcom: pm8350b: Add base dts file arm64: dts: qcom: pm8350: Add base dts file arm64: dts: qcom: pmk8350: Add base dts file arm64: dts: qcom: sm8350: Add spmi node arm64: dts: qcom: db845c: fix correct powerdown pin for WSA881x dt-bindings: arm: qcom: Add SM8350 HDK arm64: dts: qcom: sc7180: Drop duplicate dp_hot_plug_det node in trogdor arm64: dts: qcom: sm8350: fix number of pins in 'gpio-ranges' ... Link: https://lore.kernel.org/r/20210404164914.712946-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-07Merge tag 'mvebu-dt64-5.13-1' of ↵Arnd Bergmann9-15/+220
git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt mvebu dt64 for 5.13 (part 1) Add DT for fan control on SolidRun Clearfog GT8k platform Add syscon compatible to NB clk node allowing improving cpufreq support on Armada 37xx Add support for UTMI PHY allowing removing kernel dependency from the boot loader for UBS port connected to this PHY (Armada 7K, 8K and CN91xx) * tag 'mvebu-dt64-5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: arm64: dts: marvell: enable CP110 UTMI PHY usage arm64: dts: marvell: add support for Marvell CP110 UTMI PHY arm64: dts: marvell: armada-37xx: add syscon compatible to NB clk node arm64: dts: marvell: clearfog-gt-8k: add cooling maps arm64: dts: marvell: clearfog-gt-8k: add pwm-fan Link: https://lore.kernel.org/r/874kgocs7t.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-07Merge tag 'sunxi-dt-for-5.13-1' of ↵Arnd Bergmann17-57/+63
git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt Our usual bunch of patches to support the Allwinner SoCs, this time adding: - New secondary interrupt controller binding to support the wake-up - Use the RSB bus instead of I2C for the PMIC on the H6 - HDMI support for the BananaPi M2-Zero - New board: Topwise A721 * tag 'sunxi-dt-for-5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: dts: sun8i: h3: beelink-x2: Add power button arm64: dts: allwinner: h6: Use RSB for AXP805 PMIC connection ARM: dts: sunxi: h2-plus-bananapi-m2-zero: Add HDMI out ARM: dts: sun4i: Add support for Topwise A721 tablet dt-bindings: arm: Add Topwise A721 arm64: dts: allwinner: Move wakeup-capable IRQs to r_intc arm64: dts: allwinner: Use the new r_intc binding ARM: dts: sunxi: Move wakeup-capable IRQs to r_intc ARM: dts: sunxi: h3/h5: Add r_intc node ARM: dts: sunxi: Use the new r_intc binding Link: https://lore.kernel.org/r/8a3e3271-bebe-4d27-a9e7-7b7a6311a38d.lettre@localhost Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-07Merge tag 'renesas-arm-dt-for-v5.13-tag2' of ↵Arnd Bergmann7-54/+427
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.13 (take two) - Video IN (VIN) and Camera (CSI-2) support for the R-Car M3-W+ SoC, - LED support for the Falcon development board, - Preparatory display pipeline support for the R-Car V3U SoC, - Miscellaneous fixes and improvements. * tag 'renesas-arm-dt-for-v5.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: ulcb: Add cpu-supply property to a57_0 node arm64: dts: renesas: salvator-common: Add cpu-supply property to a57_0 node arm64: dts: renesas: r8a77950: Drop operating points above 1.5 GHz arm64: dts: renesas: r8a779a0: Fix PMU interrupt arm64: dts: renesas: r8a779a0: Add VSPD support arm64: dts: renesas: r8a779a0: Add FCPVD support arm64: dts: renesas: falcon-cpu: Add GP LEDs arm64: dts: renesas: r8a77961: Add VIN and CSI-2 device nodes ARM: dts: koelsch: Configure pull-up for SOFT_SW GPIO keys arm64: dts: renesas: falcon: Move AVB0 to main DTS arm64: dts: renesas: falcon: Move watchdog config to CPU board DTS arm64: dts: renesas: falcon: Move console config to CPU board DTS Link: https://lore.kernel.org/r/cover.1617359678.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-07arm64: dts: allwinner: h6: beelink-gs1: Remove ext. 32 kHz osc referenceJernej Skrabec1-4/+0
Although every Beelink GS1 seems to have external 32768 Hz oscillator, it works only on one from four tested. There are more reports of RTC issues elsewhere, like Armbian forum. One Beelink GS1 owner read RTC osc status register on Android which shipped with the box. Reported value indicated problems with external oscillator. In order to fix RTC and related issues (HDMI-CEC and suspend/resume with Crust) on all boards, switch to internal oscillator. Fixes: 32507b868119 ("arm64: dts: allwinner: h6: Move ext. oscillator to board DTs") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Tested-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210330184218.279738-1-jernej.skrabec@siol.net
2021-04-07arm64: dts: allwinner: Fix SD card CD GPIO for SOPine systemsAndre Przywara2-1/+5
Commit 941432d00768 ("arm64: dts: allwinner: Drop non-removable from SoPine/LTS SD card") enabled the card detect GPIO for the SOPine module, along the way with the Pine64-LTS, which share the same base .dtsi. However while both boards indeed have a working CD GPIO on PF6, the polarity is different: the SOPine modules uses a "push-pull" socket, which has an active-high switch, while the Pine64-LTS use the more traditional push-push socket and the common active-low switch. Fix the polarity in the sopine.dtsi, and overwrite it in the LTS board .dts, to make the SD card work again on systems using SOPine modules. Fixes: 941432d00768 ("arm64: dts: allwinner: Drop non-removable from SoPine/LTS SD card") Reported-by: Ashley <contact@victorianfox.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210316144219.5973-1-andre.przywara@arm.com
2021-04-07arm64: dts: allwinner: h6: Switch to macros for RSB clock/reset indicesChen-Yu Tsai1-2/+2
The macros for the clock and reset indices for the RSB hardware block were replaced with raw numbers when the RSB controller node was added. This was done to avoid cross-tree dependencies. Now that both the clk and DT changes have been merged, we can switch back to using the macros. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2021-04-07arm64: KVM: Enable access to TRBE support for hostSuzuki K Poulose7-5/+65
For a nvhe host, the EL2 must allow the EL1&0 translation regime for TraceBuffer (MDCR_EL2.E2TB == 0b11). This must be saved/restored over a trip to the guest. Also, before entering the guest, we must flush any trace data if the TRBE was enabled. And we must prohibit the generation of trace while we are in EL1 by clearing the TRFCR_EL1. For vhe, the EL2 must prevent the EL1 access to the Trace Buffer. The MDCR_EL2 bit definitions for TRBE are available here : https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/ Cc: Will Deacon <will@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210405164307.1720226-8-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2021-04-07KVM: arm64: Move SPE availability check to VCPU loadSuzuki K Poulose4-13/+39
At the moment, we check the availability of SPE on the given CPU (i.e, SPE is implemented and is allowed at the host) during every guest entry. This can be optimized a bit by moving the check to vcpu_load time and recording the availability of the feature on the current CPU via a new flag. This will also be useful for adding the TRBE support. Cc: Marc Zyngier <maz@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: Alexandru Elisei <Alexandru.Elisei@arm.com> Cc: James Morse <james.morse@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210405164307.1720226-7-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2021-04-07KVM: arm64: Handle access to TRFCR_EL1Suzuki K Poulose1-0/+1
Rather than falling to an "unhandled access", inject add an explicit "undefined access" for TRFCR_EL1 access from the guest. Cc: Marc Zyngier <maz@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210405164307.1720226-6-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2021-04-07Merge tag 'mvebu-fixes-5.12-1' of ↵Arnd Bergmann1-3/+3
git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/fixes mvebu fixes for 5.12 (part 1) 2 fixes on on turris-omnia (Armada 38x based:) - Fix storm interrupt - Enable hardware buffer management as it should be Unbreak AHCI on all Marvell Armada 7k8k / CN913x platforms * tag 'mvebu-fixes-5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: ARM: dts: turris-omnia: configure LED[2]/INTn pin as interrupt pin ARM: dts: turris-omnia: fix hardware buffer management Revert "arm64: dts: marvell: armada-cp110: Switch to per-port SATA interrupts" Link: https://lore.kernel.org/r/87a6qgctit.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-06arm64: dts: sdm845-db845c: make firmware filenames follow linux-firmwareDmitry Baryshkov1-2/+2
Cange aDSP and cDSP firmware filenames to follow filenames merged into linux-firmware tree. Switch from split .mdt files to merged .mbn files. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210318201405.2244723-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-04-06KVM: arm64: vgic-v3: Expose GICR_TYPER.Last for userspaceEric Auger1-19/+27
Commit 23bde34771f1 ("KVM: arm64: vgic-v3: Drop the reporting of GICR_TYPER.Last for userspace") temporarily fixed a bug identified when attempting to access the GICR_TYPER register before the redistributor region setting, but dropped the support of the LAST bit. Emulating the GICR_TYPER.Last bit still makes sense for architecture compliance though. This patch restores its support (if the redistributor region was set) while keeping the code safe. We introduce a new helper, vgic_mmio_vcpu_rdist_is_last() which computes whether a redistributor is the highest one of a series of redistributor contributor pages. With this new implementation we do not need to have a uaccess read accessor anymore. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210405163941.510258-9-eric.auger@redhat.com
2021-04-06kvm: arm64: vgic-v3: Introduce vgic_v3_free_redist_region()Eric Auger3-10/+14
To improve the readability, we introduce the new vgic_v3_free_redist_region helper and also rename vgic_v3_insert_redist_region into vgic_v3_alloc_redist_region Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210405163941.510258-8-eric.auger@redhat.com
2021-04-06KVM: arm64: Simplify argument passing to vgic_uaccess_[read|write]Eric Auger1-6/+4
vgic_uaccess() takes a struct vgic_io_device argument, converts it to a struct kvm_io_device and passes it to the read/write accessor functions, which convert it back to a struct vgic_io_device. Avoid the indirection by passing the struct vgic_io_device argument directly to vgic_uaccess_{read,write}. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210405163941.510258-7-eric.auger@redhat.com
2021-04-06KVM: arm/arm64: vgic: Reset base address on kvm_vgic_dist_destroy()Eric Auger1-1/+5
On vgic_dist_destroy(), the addresses are not reset. However for kvm selftest purpose this would allow to continue the test execution even after a failure when running KVM_RUN. So let's reset the base addresses. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210405163941.510258-5-eric.auger@redhat.com
2021-04-06KVM: arm64: vgic-v3: Fix error handling in vgic_v3_set_redist_base()Eric Auger1-1/+7
vgic_v3_insert_redist_region() may succeed while vgic_register_all_redist_iodevs fails. For example this happens while adding a redistributor region overlapping a dist region. The failure only is detected on vgic_register_all_redist_iodevs when vgic_v3_check_base() gets called in vgic_register_redist_iodev(). In such a case, remove the newly added redistributor region and free it. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210405163941.510258-4-eric.auger@redhat.com
2021-04-06KVM: arm64: Fix KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION readEric Auger1-0/+3
The doc says: "The characteristics of a specific redistributor region can be read by presetting the index field in the attr data. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3" Unfortunately the existing code fails to read the input attr data. Fixes: 04c110932225 ("KVM: arm/arm64: Implement KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION") Cc: stable@vger.kernel.org#v4.17+ Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210405163941.510258-3-eric.auger@redhat.com
2021-04-06KVM: arm64: vgic-v3: Fix some error codes when setting RDIST baseEric Auger1-7/+7
KVM_DEV_ARM_VGIC_GRP_ADDR group doc says we should return -EEXIST in case the base address of the redist is already set. We currently return -EINVAL. However we need to return -EINVAL in case a legacy REDIST address is attempted to be set while REDIST_REGIONS were set. This case is discriminated by looking at the count field. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210405163941.510258-2-eric.auger@redhat.com
2021-04-06KVM: arm64: Fix error return code in init_hyp_mode()Wang Wensheng1-1/+3
Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Fixes: eeeee7193df0 ("KVM: arm64: Bootstrap PSCI SMC handler in nVHE EL2") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wang Wensheng <wangwensheng4@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210406121759.5407-1-wangwensheng4@huawei.com
2021-04-06arm64: dts: qcom: sdm845-xiaomi-beryllium: Add DSI and panel bitsSumit Semwal1-0/+71
Enabling the Display panel for beryllium requires DSI labibb regulators and panel dts nodes to be added. It is also required to keep some of the regulators as always-on. Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org> Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210404194437.537011-1-amit.pundir@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-04-06arm64: dts: qcom: sc7280: Add Coresight supportSai Prakash Ranjan1-0/+489
Add coresight components found on SC7280 SoC. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/de07324628f88900b72357f4ef7f0c7db7e3409d.1615832893.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-04-06arm64: dts: qcom: sc7280: Add AOSS QMP nodeSai Prakash Ranjan1-0/+14
Add a DT node for the AOSS QMP on SC7280 SoC. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/12f013a09989dbc3075bfb204653dc02d54ae8a1.1615832893.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-04-06arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoCSai Prakash Ranjan1-0/+10
Add the IPCC DT node which is used to send and receive IPC signals with remoteprocs for SC7280 SoC. Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/8374f407386209d2e7891763de3fa2450a14ad60.1615832893.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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