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path: root/arch/arm64/include/asm/tlb.h
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2019-05-07Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds1-1/+4
2019-04-09arm64: mm: enable per pmd page table lockYu Zhao1-1/+4
2019-04-03asm-generic/tlb, arch: Provide generic tlb_flush() based on flush_tlb_range()Peter Zijlstra1-0/+1
2018-09-11arm64: tlb: Avoid synchronous TLBIs when freeing page tablesWill Deacon1-3/+0
2018-09-11arm64: tlb: Adjust stride and type of TLBI according to mmu_gatherWill Deacon1-9/+10
2018-09-11arm64: tlb: Remove redundant !CONFIG_HAVE_RCU_TABLE_FREE codeWill Deacon1-9/+3
2018-09-11arm64: tlbflush: Allow stride to be specified for __flush_tlb_range()Will Deacon1-1/+1
2018-08-24arm64: tlb: Provide forward declaration of tlb_flush() before including tlb.hWill Deacon1-0/+2
2018-08-01mm: do not initialize TLB stack vma's with vma_init()Linus Torvalds1-3/+1
2018-07-27mm: use vma_init() to initialize VMAs on stack and data segmentsKirill A. Shutemov1-1/+3
2015-10-07arm64: tlbflush: avoid flushing when fullmm == 1Will Deacon1-11/+15
2015-07-28arm64: Use last level TLBI for user pte changesCatalin Marinas1-1/+6
2015-04-15arm64: expose number of page table levels on Kconfig levelKirill A. Shutemov1-2/+2
2015-03-14arm64: Invalidate the TLB corresponding to intermediate page table levelsCatalin Marinas1-0/+3
2014-11-17mmu_gather: move minimal range calculations into generic codeWill Deacon1-64/+3
2014-10-10arm64: mm: enable HAVE_RCU_TABLE_FREE logicSteve Capper1-3/+17
2014-07-23arm64: Convert bool ARM64_x_LEVELS to int ARM64_PGTABLE_LEVELSCatalin Marinas1-2/+2
2014-07-23arm64: mm: Implement 4 levels of translation tablesJungseok Lee1-0/+9
2014-07-23arm64: Introduce VA_BITS and translation level optionsJungseok Lee1-1/+1
2014-04-25arm64: mm: Add THP TLB entries to general mmu_gatherSteve Capper1-0/+6
2014-02-26arm64: Convert asm/tlb.h to generic mmu_gatherCatalin Marinas1-116/+20
2013-08-16Fix TLB gather virtual address range invalidation corner casesLinus Torvalds1-2/+5
2013-06-14ARM64: mm: THP support.Steve Capper1-0/+6
2012-09-17arm64: TLB maintenance functionalityCatalin Marinas1-0/+190
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