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path: root/arch/arm64/include/asm/cacheflush.h
AgeCommit message (Expand)AuthorFilesLines
2021-07-08set_memory: allow querying whether set_direct_map_*() is actually enabledMike Rapoport1-6/+0
2021-05-25arm64: Rename arm64-internal cache maintenance functionsFuad Tabba1-18/+18
2021-05-25arm64: Fix cache maintenance function commentsFuad Tabba1-17/+30
2021-05-25arm64: sync_icache_aliases to take end parameter instead of sizeFuad Tabba1-1/+1
2021-05-25arm64: __clean_dcache_area_pou to take end parameter instead of sizeFuad Tabba1-1/+1
2021-05-25arm64: __clean_dcache_area_pop to take end parameter instead of sizeFuad Tabba1-1/+1
2021-05-25arm64: __clean_dcache_area_poc to take end parameter instead of sizeFuad Tabba1-1/+1
2021-05-25arm64: __flush_dcache_area to take end parameter instead of sizeFuad Tabba1-4/+4
2021-05-25arm64: __inval_dcache_area to take end parameter instead of sizeFuad Tabba1-1/+1
2021-05-25arm64: Do not enable uaccess for invalidate_icache_rangeFuad Tabba1-1/+1
2021-01-27arm64: cacheflush: Remove stale commentShaokun Zhang1-5/+0
2020-12-15arch, mm: make kernel_page_present() always availableMike Rapoport1-0/+1
2020-06-08arm64: use asm-generic/cacheflush.hChristoph Hellwig1-41/+5
2020-05-05arm64: cacheflush: Fix KGDB trap detectionDaniel Thompson1-3/+3
2020-02-22arm64: Ask the compiler to __always_inline functions used by KVM at HYPJames Morse1-1/+1
2019-07-08Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds1-0/+3
2019-06-24arm64/mm: wire up CONFIG_ARCH_HAS_SET_DIRECT_MAPArd Biesheuvel1-0/+3
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner1-12/+1
2018-07-05arm64: IPI each CPU after invalidating the I-cache for kernel mappingsWill Deacon1-1/+26
2018-06-16docs: Fix some broken referencesMauro Carvalho Chehab1-1/+1
2018-04-11arm64: turn flush_dcache_mmap_lock into a no-opMatthew Wilcox1-4/+2
2018-03-09arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDCShanker Donthineni1-0/+3
2018-01-08arm64: KVM: Add invalidate_icache_range helperMarc Zyngier1-0/+7
2017-11-28arm64: mm: cleanup stale AIVIVT referencesMark Rutland1-1/+1
2017-08-09arm64: Implement pmem API supportRobin Murphy1-0/+1
2017-08-09arm64: Convert __inval_cache_range() to area-basedRobin Murphy1-0/+1
2017-08-09arm64: mm: Fix set_memory_valid() declarationRobin Murphy1-1/+1
2017-05-09treewide: decouple cacheflush.h and set_memory.hLaura Abbott1-1/+0
2017-05-09treewide: move set_memory_* functions away from cacheflush.hLaura Abbott1-4/+1
2017-04-05arm64: mm: add set_memory_valid()AKASHI Takahiro1-0/+1
2016-11-23arm64: Remove I-cache invalidation from flush_cache_range()Catalin Marinas1-1/+5
2016-11-07arm64: Add uprobe supportPratyush Anand1-0/+1
2016-08-22arm64: mm: convert __dma_* routines to use start, sizeKwangwoo Lee1-1/+2
2016-03-25Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds1-7/+0
2016-03-21arm64: drop unused __local_flush_icache_all()Kefeng Wang1-7/+0
2016-02-22asm-generic: Consolidate mark_rodata_ro()Kees Cook1-4/+0
2015-12-17arm64: Use PoU cache instr for I/D coherencyAshok Kumar1-0/+1
2015-10-07arm64: flush: use local TLB and I-cache invalidationWill Deacon1-0/+7
2015-05-19arm64: kill flush_cache_all()Mark Rutland1-5/+0
2015-01-22arm64: add better page protections to arm64Laura Abbott1-0/+5
2014-12-01arm64: compat: align cacheflush syscall with arch/armVladimir Murzin1-1/+1
2014-09-08arm64: Add CONFIG_DEBUG_SET_MODULE_RONX supportLaura Abbott1-0/+4
2014-07-24arm64: Fix barriers used for page table modificationsCatalin Marinas1-10/+1
2014-05-09arm64: barriers: make use of barrier options with explicit barriersWill Deacon1-2/+2
2014-02-27arm64: Implement coherent DMA API based on swiotlbCatalin Marinas1-0/+7
2014-02-05arm64: add DSB after icache flush in __flush_icache_all()Vinayak Kale1-0/+1
2013-06-07arm64: Remove __flush_dcache_page()Catalin Marinas1-3/+0
2012-11-23arm64: Convert empty flush_cache_{mm,page} functions to static inlineCatalin Marinas1-2/+9
2012-09-17arm64: Cache maintenance routinesCatalin Marinas1-0/+148
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