summaryrefslogtreecommitdiff
path: root/arch/arm64/include/asm/cacheflush.h
AgeCommit message (Expand)AuthorFilesLines
2017-05-09treewide: decouple cacheflush.h and set_memory.hLaura Abbott1-1/+0
2017-05-09treewide: move set_memory_* functions away from cacheflush.hLaura Abbott1-4/+1
2017-04-05arm64: mm: add set_memory_valid()AKASHI Takahiro1-0/+1
2016-11-23arm64: Remove I-cache invalidation from flush_cache_range()Catalin Marinas1-1/+5
2016-11-07arm64: Add uprobe supportPratyush Anand1-0/+1
2016-08-22arm64: mm: convert __dma_* routines to use start, sizeKwangwoo Lee1-1/+2
2016-03-25Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds1-7/+0
2016-03-21arm64: drop unused __local_flush_icache_all()Kefeng Wang1-7/+0
2016-02-22asm-generic: Consolidate mark_rodata_ro()Kees Cook1-4/+0
2015-12-17arm64: Use PoU cache instr for I/D coherencyAshok Kumar1-0/+1
2015-10-07arm64: flush: use local TLB and I-cache invalidationWill Deacon1-0/+7
2015-05-19arm64: kill flush_cache_all()Mark Rutland1-5/+0
2015-01-22arm64: add better page protections to arm64Laura Abbott1-0/+5
2014-12-01arm64: compat: align cacheflush syscall with arch/armVladimir Murzin1-1/+1
2014-09-08arm64: Add CONFIG_DEBUG_SET_MODULE_RONX supportLaura Abbott1-0/+4
2014-07-24arm64: Fix barriers used for page table modificationsCatalin Marinas1-10/+1
2014-05-09arm64: barriers: make use of barrier options with explicit barriersWill Deacon1-2/+2
2014-02-27arm64: Implement coherent DMA API based on swiotlbCatalin Marinas1-0/+7
2014-02-05arm64: add DSB after icache flush in __flush_icache_all()Vinayak Kale1-0/+1
2013-06-07arm64: Remove __flush_dcache_page()Catalin Marinas1-3/+0
2012-11-23arm64: Convert empty flush_cache_{mm,page} functions to static inlineCatalin Marinas1-2/+9
2012-09-17arm64: Cache maintenance routinesCatalin Marinas1-0/+148
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-20 03:53:56 +0300