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2025-02-24arm64: dts: qcom: ipq5424: Add thermal zone nodesManikanta Mylavarapu1-0/+114
Add thermal zone nodes for sensors present in IPQ5424. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/r/20250210120436.821684-7-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-24arm64: dts: qcom: ipq5424: Add tsens nodeManikanta Mylavarapu1-0/+87
IPQ5424 has tsens v2.3.3 peripheral. This patch adds the tsens node with nvmem cells for calibration data. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/r/20250210120436.821684-6-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-24arm64: dts: qcom: ipq5332: Add thermal zone nodesPraveenkumar I1-0/+69
This patch adds thermal zone nodes for sensors present in IPQ5332. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/r/20250210120436.821684-5-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-24arm64: dts: qcom: ipq5332: Add tsens nodePraveenkumar I1-0/+66
IPQ5332 has tsens v2.3.3 peripheral. This patch adds the tsens node with nvmem cells for calibration data. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/r/20250210120436.821684-4-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-24arm64: dts: qcom: ipq6018: add LDOA2 regulatorChukun Pan1-0/+9
Add LDOA2 regulator from MP5496 to support SDCC voltage scaling. Suggested-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250210070122.208842-6-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-24arm64: dts: qcom: ipq6018: rename labels of mp5496 regulatorChukun Pan1-5/+5
Change the labels of mp5496 regulator from ipq6018 to mp5496. Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20250210070122.208842-5-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-24arm64: dts: qcom: ipq6018: move mp5496 regulator out of soc dtsiChukun Pan3-15/+36
Some IPQ60xx SoCs don't come with the mp5496 pmic chip. The mp5496 pmic was never part of the IPQ60xx SoC, it's optional, so we moved it out of the soc dtsi. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250210070122.208842-4-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-24arm64: dts: qcom: ipq6018: add 1.5GHz CPU FrequencyChukun Pan1-0/+7
The early version of IPQ6000 (SoC id: IPQ6018, SBL version: BOOT.XF.0.3-00077-IPQ60xxLZB-2) and IPQ6005 SoCs can reach a max frequency of 1.5GHz, so add this CPU frequency. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20250210070122.208842-3-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-24arm64: dts: qcom: ipq6018: add 1.2GHz CPU FrequencyChukun Pan1-0/+7
The final version of IPQ6000 (SoC id: IPQ6000, SBL version: BOOT.XF.0.3-00086-IPQ60xxLZB-1) has a max design frequency of 1.2GHz, so add this CPU frequency. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250210070122.208842-2-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-24arm64: dts: qcom: sa8775p-ride: Add firmware-name in BT nodeCheng Jiang1-0/+1
The sa8775p-ride platform uses the QCA6698 Bluetooth chip. While the QCA6698 shares the same IP core as the WCN6855, it has different RF components and RAM sizes, requiring new firmware files. Use the firmware-name property to specify the NVM and rampatch firmware to load. Signed-off-by: Cheng Jiang <quic_chejiang@quicinc.com> Reviewed-by: Zijun Hu <quic_zijuhu@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250110063914.28001-2-quic_chejiang@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-24arm64: dts: qcom: x1e80100: Mark usb_2 as dma-coherentMark Kettenis1-0/+2
Make this USB controller consistent with the others on this platform. Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes") Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250109205232.92336-1-kettenis@openbsd.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-24arm64: dts: qcom: qrb5165-rb5: enable sensors DSPDmitry Baryshkov1-0/+6
Enable SLPI, sensors DSP, on the Qualcomm Robotics RB5 platform. The firmware for the DSP is a part of linux-firmware repository. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250222-rb3-rb5-slpi-v1-2-6739be1684b6@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-24arm64: dts: qcom: sdm845-db845c: enable sensors DSPDmitry Baryshkov1-0/+6
Enable SLPI, sensors DSP, on the Qualcomm Robotics RB3 platform. The firmware for the DSP is a part of linux-firmware repository. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250222-rb3-rb5-slpi-v1-1-6739be1684b6@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-24arm64: dts: qcom: sc8280xp: Fix clock for spi0 to spi7Pengyu Luo1-8/+8
Enabling spi6 caused boot loop on my device(Huawei Matebook E Go), &spi6 { pinctrl-0 = <&spi6_default>; pinctrl-names = "default"; status = "okay"; }; After looking into this, I found the clocks for spi0 to spi7 are wrong, we can derive the correct clocks from the regular pattern between spi8 to spi15, spi16 to spi23. Or we can verify it according to the hex file of BSRC_QSPI.bin(From windows driver qcspi8280.cab) 000035d0: 0700 4445 5649 4345 0001 000a 005c 5f53 ..DEVICE.....\_S 000035e0: 422e 5350 4937 0003 0076 0001 000a 0043 B.SPI7...v.....C 000035f0: 4f4d 504f 4e45 4e54 0000 0008 0000 0000 OMPONENT........ 00003600: 0000 0000 0003 0017 0001 0007 0046 5354 .............FST 00003610: 4154 4500 0000 0800 0000 0000 0000 0000 ATE............. 00003620: 0300 3d00 0100 1400 4449 5343 4f56 4552 ..=.....DISCOVER 00003630: 4142 4c45 5f50 5354 4154 4500 0100 0600 ABLE_PSTATE..... 00003640: 434c 4f43 4b00 0100 1700 6763 635f 7175 CLOCK.....gcc_qu 00003650: 7076 335f 7772 6170 305f 7336 5f63 6c6b pv3_wrap0_s6_clk Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250223110152.47192-1-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-23arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoCSowon Na1-0/+11
Add UFS Phy for ExynosAutov920 Like ExynosAutov9, this also uses fixed-rate clock nodes until clock driver has been supported. The clock nodes are initialized on bootloader stage thus we don't need to control them so far. Changes from v4: - Place entry in correct order instead of appending to the end. Signed-off-by: Sowon Na <sowon.na@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20250219073731.853120-1-sowon.na@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-23arm64: dts: freescale: imx8mm-verdin-dahlia: add Microphone Jack to sound cardStefan Eichenberger1-3/+3
The simple-audio-card's microphone widget currently connects to the headphone jack. Routing the microphone input to the microphone jack allows for independent operation of the microphone and headphones. This resolves the following boot-time kernel log message, which indicated a conflict when the microphone and headphone functions were not separated: debugfs: File 'Headphone Jack' in directory 'dapm' already present! Fixes: 6a57f224f734 ("arm64: dts: freescale: add initial support for verdin imx8m mini") Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Cc: <stable@vger.kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-02-23arm64: dts: freescale: imx8mp-verdin-dahlia: add Microphone Jack to sound cardStefan Eichenberger1-3/+3
The simple-audio-card's microphone widget currently connects to the headphone jack. Routing the microphone input to the microphone jack allows for independent operation of the microphone and headphones. This resolves the following boot-time kernel log message, which indicated a conflict when the microphone and headphone functions were not separated: debugfs: File 'Headphone Jack' in directory 'dapm' already present! Fixes: 874958916844 ("arm64: dts: freescale: verdin-imx8mp: dahlia: add sound card") Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Cc: <stable@vger.kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-02-23arm64: dts: rockchip: disable I2C2 bus by default on RK3588 TigerQuentin Schulz1-1/+0
RK3588 Tiger routes I2C2 signals to the Q7 Camera FFC connector (P2) but nothing on the SoM itself is on that bus, therefore it'll be up to the adapter connected to the Q7 Camera FFC connector (P2) to enable the I2C2 controller, if need be. Thus, disable it by default. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-9-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: enable I2C3 in Haikou carrierboard, not Ringneck DTSIQuentin Schulz2-4/+2
PX30 Ringneck only exposes I2C3 as LVDS_BLC_CLK/DAT on Q7 golden fingers but nothing is on that bus on the SoM itself. Therefore, let's enable the I2C3 bus where it makes sense, in the Haikou carrierboard DTS. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-8-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: enable Ethernet in Haikou carrierboard, not Puma DTSIQuentin Schulz2-1/+4
The signals are exposed on Q7 golden fingers but it's not a given that the carrierboard will have an Ethernet jack. So let's move the enabling of the Ethernet controller to the carrierboard DTS instead. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-7-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: add EEPROM found on RK3399 Puma HaikouQuentin Schulz1-0/+10
The Haikou carrierboard has an EEPROM on LVDS_BLC_CLK/DAT which are signals that can carry either I2C or be used as HPD for eDP0/1. Only eDP0 is routed from RK3399 Puma SoM but only exposed on Haikou through the Video Connector, a fake PCIe connector. So to be able to use eDP one would need to use a Device Tree overlay. Therefore, let's default to having an EEPROM in Haikou carrierboard DTS. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-6-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: enable I2S0 in Haikou carrierboard, not Puma DTSIQuentin Schulz2-1/+3
I2S0 is routed to the Q7 golden fingers and, on Haikou carrierboard, to an I2S codec. Nothing aside from signal routing is done on the SoM, therefore it's the duty of the carrierboard to enable I2S0 whenever an I2S codec is present. Such is the case of the Haikou carrierboard, therefore let's migrate the enabling of this controller to the carrierboard DTS instead of the SoM DTSI. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-5-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: disable I2C6 on Puma DTSIQuentin Schulz1-1/+0
The bus is only exposed on Q7 Camera FFC connector which accepts external adapters such as Q7 Camera Demo. The enabling of I2C6 should therefore be done in the adapter Device Tree Overlay and not in the SoM DTSI, so let's disable it by default. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-4-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: move I2C6 from Haikou carrierboard to Puma DTSIQuentin Schulz2-4/+5
I2C6 is not exposed on Q7 golden fingers which is for routing signals to the carrierboard but on Q7 Camera connector, for routing signals to an additional adapter (e.g. Q7 Camera Demo adapter). Therefore, let's move the modification of I2C6 bus to Puma DTSI. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-3-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: move DDC bus from Haikou carrierboard to RK3399 Puma DTSIQuentin Schulz2-1/+4
The DDC bus is necessarily on I2C3, that's how it's exposed by RK3399 Puma on the Q7 golden fingers, so let's move it to the SoM DTSI instead. If the carrierboard doesn't route it for some reason, /delete-property/ can be used to remove it. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-2-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: enable UART5 on RK3588 Tiger HaikouQuentin Schulz1-0/+2
In its default configuration (SW2 on "UART1"), UART5 is exposed on the DB9 RS232/RS485 connector. While the same signals are also exposed on Q7_GPIO5 and Q7_GPIO6, a GPIO header, and thus could be used for other purposes, RK3399 Puma Haikou and PX30 Ringneck Haikou do enable the UART controller exposed on the DB9 connector, so let's keep consistency across our modules and enable it on RK3588 Tiger Haikou by default too. Add a comment while at it to explicit where this controller is routed to. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-1-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: Add Radxa ROCK 4D device treeStephen Chen2-0/+690
The Radxa ROCK 4D board is based on the Rockchip rk3576 SoC. The device tree adds support for basic devices: - UART - SD Card - Ethernet - USB - RTC It has 4 USB ports but only 3 are usable as the top left one is used for maskrom. It has a USB-C port that is only used for powering the board. Signed-off-by: Stephen Chen <stephen@radxa.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Link: https://lore.kernel.org/r/20250218160714.140709-3-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: add rk3576 otp nodeHeiko Stuebner1-0/+39
This adds the otp node to the rk3576 soc devicetree including the individual fields we know about. Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250210224510.1194963-7-heiko@sntech.de
2025-02-23arm64: dts: rockchip: add overlay for RK3399 Puma Haikou Video Demo adapterQuentin Schulz2-0/+171
This adds support for the video-demo-adapter DEVKIT ADDON CAM-TS-A01 (https://embedded.cherry.de/product/development-kit/) for the Haikou devkit with RK3399 Puma SoM. The Video Demo adapter is an adapter connected to the fake PCIe slot labeled "Video Connector" on the Haikou devkit. Its main feature is a Leadtek DSI-display with touchscreen and a camera (that is not supported yet because the expected clock rate by the driver cannot be exactly reached by the clock driver). To drive these components a number of additional regulators are grouped on the adapter as well as a PCA9670 gpio-expander to provide the needed additional gpio-lines. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250221-ringneck-dtbos-v2-5-310c0b9a3909@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: add overlay for PX30 Ringneck Haikou Video Demo adapterQuentin Schulz2-0/+195
This adds support for the video-demo-adapter DEVKIT ADDON CAM-TS-A01 (https://embedded.cherry.de/product/development-kit/) for the Haikou devkit with PX30 Ringneck SoM. The Video Demo adapter is an adapter connected to the fake PCIe slot labeled "Video Connector" on the Haikou devkit. Itss main feature is a Leadtek DSI-display with touchscreen and a camera (that is not supported yet because the expected clock rate by the driver cannot be exactly reached by the clock driver). To drive these components a number of additional regulators are grouped on the adapter as well as a PCA9670 gpio-expander to provide the needed additional gpio-lines. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250221-ringneck-dtbos-v2-4-310c0b9a3909@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-23arm64: dts: rockchip: add support for HAIKOU-LVDS-9904379 adapter for PX30 ↵Quentin Schulz2-0/+135
Ringneck The HAIKOU-LVDS-9904379 adapter is an adapter for PX30 Ringneck with the Haikou carrierboard. It is to be inserted in the fake PCIe slot labelled Video Connector. This adapter expects an Admatec 9904379 1024x600 LVDS display with backlight and touchscreen. An EEPROM is also found on the adapter. This adds support for this adapter on PX30 Ringneck when inserted in Haikou carrierboard. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250221-ringneck-dtbos-v2-3-310c0b9a3909@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-22arm64: dts: allwinner: a100: Add CPU Operating Performance Points tableShuosheng Huang3-0/+103
Add an Operating Performance Points table for the CPU cores to enable Dynamic Voltage & Frequency Scaling on the A100. Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com> [masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible] Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest> Link: https://patch.msgid.link/20241031070232.1793078-14-masterr3c0rd@epochal.quest Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-02-22arm64: dts: allwinner: rg35xx: Add no-thermistor property for batteryChris Morgan1-0/+1
Add the property of x-powers,no-thermistor for the battery of the Anbernic RG35XX series of H700 devices. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250204155835.161973-5-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-02-22arm64: dts: allwinner: h700: Add USB Host for RG35XX-HChris Morgan1-0/+23
The RG35XX-H has a USB host port in addition to the USB OTG port used for charging. The host port receives its power from two distinct GPIO controlled regulators. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20241018160617.157083-5-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-02-22arm64: dts: allwinner: h700: Add LED1 for Anbernic RG35XXChris Morgan1-0/+6
Add the second LED (red) to the Anbernic RG35XX series. The RG35XX has 3 LEDs: an orange one that is controlled directly by the PMIC; and a green and red one that are controlled by GPIOs. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20241018160617.157083-4-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-02-22arm64: dts: allwinner: h700: Set cpusldo to always-on for RG35XXChris Morgan1-1/+10
Set the cpusldo regulator for the AXP717 to "regulator-always-on". Its current functionality is still unknown as there are no schematics available, however it was observed that upon reboot if this regulator was disabled GPIO detection logic in the bootloader was inconsistent. Keep the regulator powered on for now until it can be defined correctly. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20241018160617.157083-3-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-02-22arm64: dts: qcom: qcs8300-ride: Enable PMIC peripheralsTingguo Cheng2-0/+52
Enable PMIC and PMIC peripherals for qcs8300-ride board. The qcs8 300-ride uses 2 pmics(pmm8620au:0,pmm8650au:1) on the board, which are variants of pmm8654au used on sa8775p/qcs9100 -ride(4x pmics). Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Tingguo Cheng <quic_tingguoc@quicinc.com> Link: https://lore.kernel.org/r/20250108-adds-spmi-pmic-peripherals-for-qcs8300-v3-2-ee94642279ff@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-22arm64: dts: qcom: qcs8300: Adds SPMI supportTingguo Cheng1-0/+22
Add the SPMI bus arbiter(Version:5.2.0) node for QCS8300 SoC which connected with PMICs on QCS8300 boards. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Tingguo Cheng <quic_tingguoc@quicinc.com> Link: https://lore.kernel.org/r/20250108-adds-spmi-pmic-peripherals-for-qcs8300-v3-1-ee94642279ff@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-22arm64: dts: qcom: qcm2290: Add uart3 nodeWojciech Slenska1-0/+24
Add node to support uart3. Signed-off-by: Wojciech Slenska <wojciech.slenska@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241112124651.215537-1-wojciech.slenska@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-22arm64: dts: qcom: qcs6490-rb3gen2: add and enable BT nodeJanaki Ramaiah Thota1-1/+170
Add the PMU node for WCN6750 present on the qcs6490-rb3gen2 board and assign its power outputs to the Bluetooth module. In WCN6750 module sw_ctrl and wifi-enable pins are handled in the wifi controller firmware. Therefore, it is not required to have those pins' entries in the PMU node. Signed-off-by: Janaki Ramaiah Thota <quic_janathot@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250221171014.120946-2-quic_janathot@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-22arm64: dts: qcom: sm8650: add cpu OPP table with DDR, LLCC & L3 bandwidthsNeil Armstrong1-0/+876
Add the OPP tables for each CPU clusters (cpu0-1, cpu2-3-4, cpu5-6 & cpu7) to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache frequency by aggregating bandwidth requests of all CPU core with referenc to the current OPP they are configured in by the LMH/EPSS hardware. The effect is a proper caches & DDR frequency scaling when CPU cores changes frequency. The OPP tables were built using the downstream memlat ddr, llcc & l3 tables for each cluster types with the actual EPSS cpufreq LUT tables from running HDK and QRD devices. The cpu2 and cpu5 tables are similar but must be kept separate to take in account that they define OPP for shared CPUs of two different clusters that can scale separately, thus vote different bandwidths. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-3-a0c950540e68@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-22arm64: dts: qcom: sm8650: add cpu interconnect nodesNeil Armstrong1-0/+57
Add the interconnect entry for each cpu, with 3 different paths: - CPU to Last Level Cache Controller (LLCC) - Last Level Cache Controller (LLCC) to DDR - L3 Cache from CPU to DDR interface Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-2-a0c950540e68@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-22arm64: dts: qcom: sm8650: add OSM L3 nodeNeil Armstrong1-0/+10
Add the OSC L3 Cache controller node. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-1-a0c950540e68@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-22arm64: dts: qcom: x1e80100: Add the watchdog deviceRajendra Nayak1-0/+7
The X Elite implements Server Base System Architecture (SBSA) specification compliant generic watchdog. Describe it. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20250212-x1e80100-add-watchdog-v2-1-a73897f0dad5@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-22arm64: dts: qcom: qcs6490-rb3gen2: Add vadc and adc-tm channelsRakesh Kota1-0/+108
Add support for vadc and adc-tm channels which are used for monitoring thermistors present on the platform. - Add the necessary includes for qcom,spmi-adc7-pm7325 and qcom,spmi-adc7-pmk8350. - Add thermal zones for quiet-thermal, sdm-skin-thermal, and xo-thermal, and define their polling delays and thermal sensors. - Configure the pm7325_temp_alarm node to use the pmk8350_vadc channel for thermal monitoring. - Configure the pmk8350_adc_tm node to enable its thermal sensors and define their registers and settings. - Configure the pmk8350_vadc node to define its channels and settings Signed-off-by: Rakesh Kota <quic_kotarake@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250212113342.873086-1-quic_kotarake@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-21arm64: dts: renesas: rzg2: Add boot phase tagsMarek Vasut7-0/+34
bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Add bootph-all for all nodes that are used in the bootloader on Renesas RZ/G2 SoCs. All SoC require CPG clock and its input clock, RST Reset, PFC pin control and PRR ID register access during all stages of the boot process, those are marked using bootph-all property, and so is the SoC bus node which contains these IP. Each board console UART is also marked as bootph-all to make it available in all stages of the boot process. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250209180616.160253-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: rcar: Add boot phase tagsMarek Vasut25-0/+104
bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Add bootph-all for all nodes that are used in the bootloader on Renesas R-Car SoCs. All SoC require CPG clock and its input clock, RST Reset, PFC pin control and PRR ID register access during all stages of the boot process, those are marked using bootph-all property, and so is the SoC bus node which contains these IP. Each board console UART is also marked as bootph-all to make it available in all stages of the boot process. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250209180616.160253-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: white-hawk-csi-dsi: Use names for CSI-2 data line ordersNiklas Söderlund1-2/+6
The symbolic names for the line-orders are now available in <dt-bindings/media/video-interfaces.h>. Switch to them instead of using their numerical values. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250205103311.668768-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: ulcb/kf: Use TDM Split Mode for captureKuninori Morimoto3-26/+166
Current ulcb/kf of -mix+split.dtsi is using TDM Split Mode, but only for playback. Use TDM Split Mode on capture too. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/875xlrshp5.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: Add initial support for MYIR Remi PiJulien Massot2-0/+340
Add basic support for the MYIR Remi Pi (based on r9a07g044l2): - UART, - I2C, - eMMC, - USB host, - HDMI output, - Ethernet. Signed-off-by: Julien Massot <julien.massot@collabora.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250131-myir-remi-pi-v3-2-2dda53e79291@collabora.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-30 14:53:35 +0300