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2025-02-21arm64: dts: renesas: r9a08g045: Add OPP tableClaudiu Beznea1-0/+28
Add OPP table for the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250128145616.2691841-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: r9a09g057: Enable SYS nodeJohn Madieu1-1/+0
SoC identification needs the System Controller. Enable it. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250123170508.13578-10-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: r9a09g047: Add SYS nodeJohn Madieu1-0/+7
Add a node for the System Controller to the RZ/G3E (R9A09G047) SoC DTSI, as it is also required for SoC identification. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250123170508.13578-9-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: r9a08g045: Enable SYS nodeClaudiu Beznea1-1/+0
Enable the System Controller. It is needed for SoC identification. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250123170508.13578-8-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: r8a779f0: Disable rswitch ports by defaultGeert Uytterhoeven3-4/+8
The Renesas Ethernet Switch has three independent ports. Each port can act as a separate interface, and can be enabled or disabled independently. Currently all ports are enabled by default, hence board DTS files that enable the switch must disable all unused ports explicitly. Disable all ports by default, and explicitly enable ports that are used, next to their configuration. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://lore.kernel.org/c4688de8e3289ad82c2cd85f0893eac660ac8890.1737649969.git.geert+renesas@glider.be
2025-02-21arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1Claudiu Beznea4-0/+60
Add a DT overlay for SCIF1 (of the Renesas RZ/G3S SoC) routed through the PMOD1_3A interface available on the Renesas RZ SMARC Carrier II board. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250120130936.1080069-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: rzg3s-smarc: Enable SCIF3Claudiu Beznea1-0/+12
Enable SCIF3. It is routed to the SER1_UART interface on the RZ SMARC Carrier II board. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250120130936.1080069-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe ↵Claudiu Beznea2-19/+33
different switches There are different switches available on both the RZ/G3S SMARC Module and RZ SMARC Carrier II boards. These switches are used to route different SoC signals to different parts available on board. These switches are described in device trees through macros. These macros are set accordingly such that the resulted compiled dtb to describe the on-board switches states. The SCIF1 depends on the state of the SW_CONFIG3 and SW_OPT_MUX4 switches. SCIF1 can be enabled through a device tree overlay. To manage all switches in a unified state and allow users to configure the output device tree, add a file that contains all switch definitions and states. Commit prepares the code to enable SCIF1 on the RZ/G3S overlay. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250120130936.1080069-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: r8a779g0: Restore sort orderGeert Uytterhoeven1-40/+40
Numerical by unit address, but grouped by type. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/ccd215c1146b84c085908e01966f7036be51afa8.1737370801.git.geert+renesas@glider.be
2025-02-21arm64: dts: renesas: s4sk: Fix ethernet0 alias for rswitchMarek Vasut1-1/+2
Each rswitch port TSNn has a dedicated MAC address assigned to it, so does AVB MAC. The MAC addresses for each rswitch port and AVB, four in total, are stored in the FPGA populated on the board and can be read out via I2C from bus i2c@e66e0000 address 0x70 offsets 0x58 for AVB and 0x60, 0x68, 0x70 for TSNn. There is no single MAC address assigned to the rswitch itself, there are three of them, one for each rswitch port. Instead of ethernet0 alias for rswitch itself, describe aliases ethernet0, ethernet1 for each enabled rswitch port. This allows U-Boot to insert MAC addresses from its environment variables ethaddr/eth1addr/eth2addr into each rswitch port nodes, so Linux can read and use one unique MAC address for each rswitch port. Note that it is unlikely this would break existing rswitch driver operation in the Linux kernel, because as of right now, the rswitch driver already calls of_get_ethdev_address() for each port to read out the MAC address of each rswitch port DT node. If that is missing, it falls back to MAC address settings read from the hardware itself. If that also fails, it uses a random MAC address. Fixes: 412f2224b3b6 ("arm64: dts: renesas: s4sk: Fix ethernet0 alias") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250118111344.361617-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: spider-ethernet: Add ethernetN aliases for rswitchMarek Vasut1-0/+8
The rswitch has three independent ports which each can act as a separate interface with its own MAC address. Describe DT aliases ethernet0, ethernet1, ethernet2 for each rswitch port in DT. This allows U-Boot to insert MAC addresses from its environment variables ethaddr/eth1addr/eth2addr into each rswitch port nodes, so Linux can read and use one unique MAC address for each rswitch port. Note that it is unlikely this would break existing rswitch driver operation in the Linux kernel, because as of right now, the rswitch driver already calls of_get_ethdev_address() for each port to read out the MAC address of each rswitch port DT node. If that is missing, it falls back to MAC address settings read from the hardware itself. If that also fails, it uses a random MAC address. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250118111344.361617-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: s4sk: Access rswitch ports via phandlesMarek Vasut1-36/+31
The r8a779f0.dtsi now contains labels for each rswitch port in the form 'rswitch_portN'. Use those to access rswitch ports and slightly reduce the depth of this board DT. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250118111344.361617-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: spider-ethernet: Access rswitch ports via phandlesMarek Vasut1-45/+42
The r8a779f0.dtsi now contains labels for each rswitch port in the form 'rswitch_portN'. Use those to access rswitch ports and slightly reduce the depth of this board DT. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250118111344.361617-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: r8a779f0: Add labels for rswitch portsMarek Vasut1-3/+3
Introduce labels for each rswitch port in the form 'rswitch_portN'. Those can be used to access rswitch port nodes directly, which is going to be useful in reducing DT indentation slightly as well as in the DT /aliases node to reference the rswitch ports as ethernetN interfaces. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250118111344.361617-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: Add initial device tree for Yuridenki-Shokai Kakip boardNobuhiro Iwamatsu2-0/+137
Add basic support for the Yuridenki-Shokai Kakip board based on R9A09G057H48, including: - Memory - OSTM0 - OSTM7 - Pin Control - Input clocks - SCIF - SDHI0 Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250116144752.1738574-5-iwamatsu@nigauri.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: eagle-function-expansion: Align GPIO hog name with bindingsKrzysztof Kozlowski1-1/+1
Bindings expect GPIO hog names to end with 'hog' suffix, so correct it to fix dtbs_check warning: r8a77970-eagle-function-expansion.dtb: gpio@27: 'vin0_adv7612_en' does not match any of the regexes: '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115211755.194219-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: r8a779h0: Add VSPX instanceNiklas Söderlund1-0/+11
Add device node for the VSPX instance on R-Car V4M. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115181050.3728275-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: r8a779h0: Add FCPVX instanceNiklas Söderlund1-0/+9
Add device node for the FCPVX instance on R-Car V4M. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115181050.3728275-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: rzg3e-smarc-som: Enable watchdogBiju Das1-0/+4
Enable WDT1 watchdog on RZ/G3E SMARC SoM platform. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115103858.104709-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: r9a09g047: Add WDT1-WDT3 nodesBiju Das1-0/+30
Add WDT1-WDT3 nodes to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250115103858.104709-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: gray-hawk-single: Restore sort orderGeert Uytterhoeven1-19/+19
Alphabetical by label name. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/4f3e057b9a73d7ee7ff073f51bb9a4c30bdd0c84.1736506813.git.geert+renesas@glider.be
2025-02-21arm64: dts: renesas: r8a779a0: Add VSPX instancesNiklas Söderlund1-0/+44
Add device nodes for the VSPX instances on R-Car V3U. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250109125433.2402045-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: r8a779a0: Add FCPVX instancesNiklas Söderlund1-0/+36
Add device nodes for the FCPVX instances on R-Car V3U. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250109125433.2402045-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: gray-hawk-single: Describe AVB1 and AVB2Niklas Söderlund1-0/+94
Describe the two Marvell 88Q2110/QFN40 PHYs available on the R-Car V4M Gray Hawk single-board. The two PHYs are wired up on the board by default. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250107160127.528933-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: r8a779h0: Remove #address- and #size-cells from AVB[0-2]Niklas Söderlund2-14/+13
When describing the PHYs connected to AVB1 and AVB2, mdio nodes will be needed to describe the connections, and each mdio node will need to contain these two properties instead. This will make the #address-cells and #size-cells described in the base SoC include file redundant and they will produce warnings, remove them. In an effort to keep all three AVB nodes style consistent add an mdio node to AVB0 already described and rename the phy node to better describe the PHY that is connected to AVB0 before adding more PHYs. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250107160127.528933-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-21arm64: dts: renesas: r8a77990: Re-add voltages to OPP tableGeert Uytterhoeven1-0/+4
When CONFIG_ENERGY_MODEL=y: cpu cpu0: EM: invalid perf. state: -22 When removing the (incorrect) voltages from the Operating Points Parameters tables, it was assumed they were optional, and unused, when none of the CPU nodes is tied to a regulator using the "cpu-supply" property. This assumption turned out to be incorrect, causing the reported error message. Fix this by re-adding the (correct) voltages. Note that because all voltages are identical, all operating points are considered to have the same efficiency, and the energy model always picks the one with the highest clock rate. Reported-by: Renesas Test Team via Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Fixes: fb76b0fae3ca8803 ("arm64: dts: renesas: r8a77990: Remove bogus voltages from OPP table") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/80890bc244670bc3e8d6fc89fb2c3cb23e7025f5.1728377971.git.geert+renesas@glider.be
2025-02-21arm64: dts: renesas: r8a774c0: Re-add voltages to OPP tableGeert Uytterhoeven1-0/+4
When CONFIG_ENERGY_MODEL=y: cpu cpu0: EM: invalid perf. state: -22 When removing the (incorrect) voltages from the Operating Points Parameters tables, it was assumed they were optional, and unused, when none of the CPU nodes is tied to a regulator using the "cpu-supply" property. This assumption turned out to be incorrect, causing the reported error message. Fix this by re-adding the (correct) voltages. Note that because all voltages are identical, all operating points are considered to have the same efficiency, and the energy model always picks the one with the highest clock rate. Reported-by: Renesas Test Team via Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Fixes: 554edc3e9239bb81 ("arm64: dts: renesas: r8a774c0: Remove bogus voltages from OPP table") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/2046da75f3db95b62f86c0482063c4d04c2b47d5.1728377971.git.geert+renesas@glider.be
2025-02-21arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC ITS instead of MBIDmitry Osipenko1-1/+1
Rockchip 356x device-tree now supports GIC ITS. Move PCIe controller's MSI to use ITS instead of MBI. This removes extra CPU overhead of handling PCIe MBIs by letting GIC's ITS to serve the PCIe MSIs. Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250216221634.364158-4-dmitry.osipenko@collabora.com
2025-02-21arm64: dts: rockchip: rk356x: Add MSI controller nodeDmitry Osipenko1-0/+12
Rockchip 356x SoC's GIC has two hardware integration issues that affect MSI functionality of the GIC. Previously, both these GIC issues were worked around by using MBI for MSI instead of ITS because kernel GIC driver didn't have necessary quirks. First issue is about RK356x GIC not supporting programmable shareability, while reporting it as supported in a GIC's feature register. Rockchip assigned Erratum ID #3568001 for this issue. This patch adds dma-noncoherent property to the GIC node, denoting that a SW workaround is required for mitigating the issue. Second issue is about GIC AXI master interface addressing limited to the first 4GB of physical address space. Rockchip assigned Erratum ID #3568002 for this issue. Now that kernel supports quirks for both of the erratums, add MSI controller node to RK356x device-tree. Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250216221634.364158-3-dmitry.osipenko@collabora.com
2025-02-21arm64: zynqmp: Use DT header for firmware constantsMichal Simek2-1/+127
Firmware contants do not fit the purpose of bindings because they are not independent IDs for abstractions. They are more or less just contants which better to wire via header with DT which is using it. That's why copy header to platform folder (align macro) and use it locally. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c3f011812597f4c3095448726f5924b2334c7da1.1738600745.git.michal.simek@amd.com
2025-02-20arm64: dts: rockchip: remove supports-cqe from rk3588 tigerHeiko Stuebner1-1/+0
The sdhci controller supports cqe it seems and necessary code also is in place - in theory. At this point Jaguar and Tiger are the only boards enabling cqe support on the rk3588 and we are seeing reliability issues under load. This can be caused by either a controller-, hw- or driver-issue and definitly needs more investigation to work properly it seems. So disable cqe support on Tiger for now. Fixes: 6173ef24b35b ("arm64: dts: rockchip: add RK3588-Q7 (Tiger) SoM") Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250219093303.2320517-2-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-20arm64: dts: rockchip: remove supports-cqe from rk3588 jaguarHeiko Stuebner1-1/+0
The sdhci controller supports cqe it seems and necessary code also is in place - in theory. At this point Jaguar and Tiger are the only boards enabling cqe support on the rk3588 and we are seeing reliability issues under load. This can be caused by either a controller-, hw- or driver-issue and definitly needs more investigation to work properly it seems. So disable cqe support on Jaguar for now. Fixes: d1b8b36a2cc5 ("arm64: dts: rockchip: add Theobroma Jaguar SBC") Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250219093303.2320517-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-18arm64: dts: apple: Add SPI NOR nvram partition to all devicesJanne Grunau5-0/+47
All known M1* and M2* devices use an identical SPI NOR flash configuration with a partition containing a non-volatile key:value storage. Use a .dtsi and include it for every device. The nvram partition parameters itself depend on the version of the installed Apple iboot boot loader. m1n1 will fill in the current values provided by Apple's iboot. Reviewed-by: Neal Gompa <neal@gompa.dev> Signed-off-by: Janne Grunau <j@jannau.net> Link: https://lore.kernel.org/r/20241203-asahi-spi-dt-v2-5-cd68bfaf0c84@jannau.net Signed-off-by: Sven Peter <sven@svenpeter.dev>
2025-02-18arm64: dts: apple: t600x: Add spi controller nodesJanne Grunau3-0/+49
Apple silicon devices have one or more SPI devices. Add device tree nodes for all known controllers. The missing ones could be guessed and tested with a little effort but since the devices expose no pins and no new devices are expected there is no point in spending the effort. SPI is used for spi-nor and input devices like keyboard, trackpad, touchscreen and fingerprint reader. Only the spi-nor flash has upstream drivers. Support for it will be added in a following commit. Reviewed-by: Neal Gompa <neal@gompa.dev> Signed-off-by: Janne Grunau <j@jannau.net> Link: https://lore.kernel.org/r/20241203-asahi-spi-dt-v2-4-cd68bfaf0c84@jannau.net Signed-off-by: Sven Peter <sven@svenpeter.dev>
2025-02-18arm64: dts: apple: t8112: Add spi controller nodesJanne Grunau1-1/+43
Apple silicon devices have one or more SPI devices. Add device tree nodes for all known controllers. The missing ones could be guessed and tested with a little effort but since the devices expose no pins and no new devices are expected there is no point in spending the effort. SPI is used for spi-nor and input devices like keyboard, trackpad, touchscreen and fingerprint reader. Only the spi-nor flash has upstream drivers. Support for it will be added in a following commit. Reviewed-by: Neal Gompa <neal@gompa.dev> Signed-off-by: Janne Grunau <j@jannau.net> Link: https://lore.kernel.org/r/20241203-asahi-spi-dt-v2-3-cd68bfaf0c84@jannau.net Signed-off-by: Sven Peter <sven@svenpeter.dev>
2025-02-18arm64: dts: apple: t8103: Add spi controller nodesJanne Grunau1-0/+76
Apple silicon devices have one or more SPI devices. Add device tree nodes for all known controllers. The missing ones could be guessed and tested with a little effort but since the devices expose no pins and no new devices are expected there is no point in spending the effort. SPI is used for spi-nor and input devices like keyboard, trackpad, touchscreen and fingerprint reader. Only the spi-nor flash has upstream drivers. Support for it will be added in a following commit. Reviewed-by: Neal Gompa <neal@gompa.dev> Signed-off-by: Janne Grunau <j@jannau.net> Link: https://lore.kernel.org/r/20241203-asahi-spi-dt-v2-2-cd68bfaf0c84@jannau.net Signed-off-by: Sven Peter <sven@svenpeter.dev>
2025-02-18arm64: dts: apple: t8103: Fix spi4 power domain sort orderHector Martin1-9/+9
Signed-off-by: Hector Martin <marcan@marcan.st> Reviewed-by: Neal Gompa <neal@gompa.dev> Link: https://lore.kernel.org/r/20241203-asahi-spi-dt-v2-1-cd68bfaf0c84@jannau.net Signed-off-by: Sven Peter <sven@svenpeter.dev>
2025-02-18arm64: dts: apple: t7000: Add missing CPU p-state 7 for J96 and J97Nick Chan2-0/+10
Add missing CPU p-state 7 @ 1512 MHz for iPad mini 4. Fixes: e97323994f4a ("arm64: dts: apple: t7000: Add cpufreq nodes") Signed-off-by: Nick Chan <towinchenmi@gmail.com> Link: https://lore.kernel.org/r/20250217-mini4-cpufreq-v1-1-8974e90dd806@gmail.com Signed-off-by: Sven Peter <sven@svenpeter.dev>
2025-02-18arm64: dts: mediatek: mt6359: fix dtbs_check error for audio-codecMacpaul Lin1-1/+2
This change fixes these dtbs_check errors for audio-codec: 1. pmic: 'mt6359codec' does not match any of the regexes: 'pinctrl-[0-9]+' - Replace device node name to generic 'audio-codec' 2. pmic: regulators: 'compatible' is a required property - Add 'mediatek,mt6359-codec' to compatible. Fixes: 3b7d143be4b7 ("arm64: dts: mt6359: add PMIC MT6359 related nodes") Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250217113736.1867808-1-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-02-18arm64: dts: freescale: tqma8mpql: Fix vqmmc-supplyAlexander Stein1-12/+4
eMMC is supplied by BUCK5 rail. Use the actual regulator instead of a virtual fixed regulator. Fixes: 418d1d840e421 ("arm64: dts: freescale: add initial device tree for TQMa8MPQL with i.MX8MP") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-02-17arm64: versal-net: Add description for b2197-00 revA boardMichal Simek4-0/+1101
Add description for VN-X board. The board is using Versal NET SoC which has 16 a78 cores with additional IPs. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1b23d64107220f5b48fc77ba28c5e59a20d83600.1738657826.git.michal.simek@amd.com
2025-02-17arm64: dts: imx95-19x19-evk: add typec nodes and enable usb3 nodeXu Yang1-0/+83
This board has one Type-C port which has USB3 capability. This will add typec nodes and enable usb3 node. Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-02-17arm64: dts: imx95: add usb3 related nodesXu Yang1-0/+42
Add usb3 phy and controller nodes for imx95. Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-02-17arm64: dts: imx8qm-mek: add audio-codec cs42888 and related nodesFrank Li1-0/+80
Add audio-codec cs42888, enable esai0 and asrc0. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-02-17arm64: dts: imx8mq-librem5: remove undocument property 'extcon' for usb-pd@3fFrank Li1-1/+0
Remove undocment property 'extcon' for usb-pd@3f to fix below CHECK_DTBS warnings: arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dtb: usb-pd@3f: 'extcon' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/usb/ti,tps6598x.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-02-17arm64: dts: exynosautov920: add CPU cache informationDevang Tailor1-0/+127
Add CPU caches information to its dt nodes so that the same is available to userspace via sysfs. This SoC has 64/64 KB I/D cache and 256KB of L2 cache for each core, 2 MB of shared L3 cache for each quad cpu cluster and 1 MB of shared L3 cache for the dual cpu cluster. Signed-off-by: Devang Tailor <dev.tailor@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20250108055012.1938530-1-dev.tailor@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-16arm64: dts: rockchip: Add rng node to RK3588Nicolas Frattaroli1-0/+8
Add the RK3588's standalone hardware random number generator node to its device tree, and enable it. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250204-rk3588-trng-submission-v2-6-608172b6fd91@collabora.com [changed reset-id to its numeric value while the constant makes its way through the crypto tree] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-16arm64: dts: exynos: gs101: add ACPM protocol nodeTudor Ambarus1-0/+8
Add the ACPM protocol node. ACPM protocol provides interface for all the client drivers making use of the features offered by the Active Power Management (APM) module. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20250207-gs101-acpm-dt-v4-3-230ba8663a2d@linaro.org [krzysztof: correct alphabetical node placement] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-16arm64: dts: exynos: gs101: add AP to APM mailbox nodeTudor Ambarus1-0/+9
GS101 has 14 mailbox controllers. Add the AP to APM mailbox node. Mailbox controllers have a shared register that can be used for passing the mailbox messages. The AP to APM mailbox controller is used just as a doorbell mechanism. It raises interrupt to the firmware after the mailbox message has been written to SRAM where the TX/RX rings are defined. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20250207-gs101-acpm-dt-v4-2-230ba8663a2d@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-16arm64: dts: exynos: gs101: add SRAM nodeTudor Ambarus1-0/+8
SRAM is used by the ACPM protocol to retrieve the ACPM channels information, which includes the TX/RX rings among other channel configuration data. Add the SRAM node. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20250207-gs101-acpm-dt-v4-1-230ba8663a2d@linaro.org [krzysztof: correct alphabetical node placement] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-01 08:37:17 +0300