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2024-06-08arm64: dts: qcom: ipq9574-*: Remove thermal zone polling delaysKonrad Dybcio1-26/+0
All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-3-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-08arm64: dts: qcom: ipq8074-*: Remove thermal zone polling delaysKonrad Dybcio1-12/+0
All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-2-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-08arm64: dts: qcom: ipq6018-*: Remove thermal zone polling delaysKonrad Dybcio1-6/+0
All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-1-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: sc8280xp-crd: use external pull up for touch resetJohan Hovold1-2/+1
The touch controller reset line is currently not described by the devicetree except in the pin configuration which is used to deassert reset. As the reset line has an external pull up to an always-on rail there is no need to drive the pin high so just leave it configured as an input and disable the internal pull down. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20240507144821.12275-7-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: sc8280xp-x13s: fix touchscreen power onJohan Hovold1-7/+8
The Elan eKTH5015M touch controller on the X13s requires a 300 ms delay before sending commands after having deasserted reset during power on. Switch to the Elan specific binding so that the OS can determine the required power-on sequence and make sure that the controller is always detected during boot. Note that the always-on 1.8 V supply (s10b) is not used by the controller directly and should not be described. Fixes: 32c231385ed4 ("arm64: dts: qcom: sc8280xp: add Lenovo Thinkpad X13s devicetree") Cc: stable@vger.kernel.org # 6.0 Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20240507144821.12275-6-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: sc7180-trogdor: Make clamshell/detachable fragmentsStephen Boyd11-31/+31
At a high-level, detachable Trogdors (sometimes known as Strongbads) don't have a cros_ec keyboard, while all clamshell Trogdors (only known as Trogdors) always have a cros_ec keyboard. Looking closer though, all clamshells have a USB type-A connector and a hardwired USB camera. And all detachables replace the USB camera with a MIPI based one and swap the USB type-a connector for the detachable keyboard pogo pins. Split the detachable and clamshell bits into different files so we can describe these differences in one place instead of in each board that includes sc7180-trogdor.dtsi. For now this is just the keyboard part, but eventually this will include the type-a port and the pogo pins. Cc: cros-qcom-dts-watchers@chromium.org Cc: Bjorn Andersson <andersson@kernel.org> Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: Pin-yen Lin <treapking@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20240604214233.3551692-4-swboyd@chromium.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: sc7180: pazquel: Add missing comment headerStephen Boyd1-0/+2
We put a header before modifying pinctrl nodes defined in sc7180-trogdor.dtsi in every other file. Add one here so we know that this section is for pinctrl modifications. Cc: cros-qcom-dts-watchers@chromium.org Cc: Bjorn Andersson <andersson@kernel.org> Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: Pin-yen Lin <treapking@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20240604214233.3551692-3-swboyd@chromium.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: sc7180: quackingstick: Disable instead of delete usb_c1Stephen Boyd1-3/+5
It's simpler to reason about things if we disable nodes instead of deleting them. Disable the second usb type-c connector node on quackingstick instead of deleting it so that we can reason about ports more easily. Cc: cros-qcom-dts-watchers@chromium.org Cc: Bjorn Andersson <andersson@kernel.org> Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: Pin-yen Lin <treapking@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20240604214233.3551692-2-swboyd@chromium.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: sm8450-sony-xperia: correct touchscreen interrupt flagsKrzysztof Kozlowski1-1/+1
Interrupt flags 0x2008 looks like some downstream copy-paste, because generic GPIOLIB code, used by Qualcomm pin controller drivers, ignores flags outside of IRQ_TYPE_SENSE_MASK. Probably the intention was to pass just 0x8, so IRQ_TYPE_LEVEL_LOW. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # SM8450 PDX223 Link: https://lore.kernel.org/r/20240605160032.150587-4-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: sm8250-sony-xperia: correct touchscreen interrupt flagsKrzysztof Kozlowski1-1/+1
Interrupt flags 0x2008 looks like some downstream copy-paste, because generic GPIOLIB code, used by Qualcomm pin controller drivers, ignores flags outside of IRQ_TYPE_SENSE_MASK. Probably the intention was to pass just 0x8, so IRQ_TYPE_LEVEL_LOW. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240605160032.150587-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: sm6375-pdx225: correct touchscreen interrupt flagsKrzysztof Kozlowski1-1/+1
Interrupt flags 0x2008 looks like some downstream copy-paste, because generic GPIOLIB code, used by Qualcomm pin controller drivers, ignores flags outside of IRQ_TYPE_SENSE_MASK. Probably the intention was to pass just 0x8, so IRQ_TYPE_LEVEL_LOW. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240605160032.150587-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: sm6350-pdx213: correct touchscreen interrupt flagsKrzysztof Kozlowski1-1/+1
Interrupt flags 0x2008 looks like some downstream copy-paste, because generic GPIOLIB code, used by Qualcomm pin controller drivers, ignores flags outside of IRQ_TYPE_SENSE_MASK. Probably the intention was to pass just 0x8, so IRQ_TYPE_LEVEL_LOW. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240605160032.150587-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: x1e80100-qcp: Add pmic-glink node with all 3 connectorsAbel Vesa1-0/+119
Add the pmic-glink node and describe all 3 USB Type-C connectors. Do this for USB only, for now. The DP ports will come at a later stage since they use muxes. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240606-x1e80100-dts-pmic-glink-v2-3-972c902e3e6b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: x1e80100-crd: Add pmic-glink node with all 3 connectorsAbel Vesa1-0/+122
Add the pmic-glink node and describe all 3 USB Type-C connectors. Do this for USB only, for now. The DP ports will come at a later stage since they use retimers. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240606-x1e80100-dts-pmic-glink-v2-2-972c902e3e6b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07arm64: dts: qcom: x1e80100: Add remote endpoints between PHYs and DPsAbel Vesa1-0/+9
Describe the port/endpoints graph between the USB/DP combo PHYs and their corresponding DP controllers. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240606-x1e80100-dts-pmic-glink-v2-1-972c902e3e6b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-07Merge branch 'arm64-fixes-for-6.10' into arm64-for-6.11Bjorn Andersson6-9/+34
Merge the arm64-fixes-for-6.10 branch into arm64-for-6.11 to resolve the merge conflict caused by pmic-glink and reserved-memory introduction at the same place in the x1e80100 crd and qcp dts files.
2024-06-06arm64: dts: sm8650-hdk: add support for the Display Card overlayNeil Armstrong2-0/+145
With the SM8650-HDK, a Display Card kit can be connected to provide a VTDR6130 display with Goodix Berlin Touch controller. In order to route the DSI lanes to the connector for the Display Card kit, a switch must be changed on the board. The HDMI nodes are disabled since the DSI lanes are shared with the DSI to HDMI transceiver. Add support for this card as an overlay and apply it it at build-time to the sm8650-hdk dtb. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Tested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240606-topic-sm8650-upstream-hdk-v6-1-fb034fe864cc@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06arm64: dts: qcom: pm660: Add rradc, chargerAboothahir U1-0/+25
Add charger to PM660 PMIC. Readings from round-robin ADC are needed for charger to function, so add it as well. Signed-off-by: Aboothahir U <aboothahirpkd@gmail.com> Signed-off-by: Barnabás Czémán <trabarni@gmail.com> Link: https://lore.kernel.org/r/20240606-pm660-charger-rrdac-v1-1-a95d4da24f3b@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06arm64: dts: qcom: x1e80100: Fix PCIe 6a reg offsets and add MHIAbel Vesa1-4/+6
The actual size of the DBI region is 0xf20 and the start of the ELBI region is 0xf40, according to the documentation. So fix them. While at it, add the MHI region as well. Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240604-x1e80100-dts-fixes-pcie6a-v2-1-0b4d8c6256e5@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add PMIC and chargerRaymond Hackley5-0/+106
The phones listed below have Richtek RT5033 PMIC and charger. Add them to the device trees. - Samsung Galaxy Core Prime LTE - Samsung Galaxy Grand Prime Cc: Jakob Hauser <jahau@rocketmail.com> Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com> Link: https://lore.kernel.org/r/20240601115321.25314-4-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add S3FWRN5 NFCRaymond Hackley3-0/+37
Some variants of Samsung Galaxy Core Prime LTE / Grand Prime LTE have a Samsung S3FWRN5 NFC chip that works quite well with the s3fwrn5 driver in the Linux NFC subsystem. The clock setup for the NFC chip is a bit special (although this seems to be a common approach used for Qualcomm devices with NFC): The NFC chip has an output GPIO that is asserted whenever the clock is needed to function properly. On the A3/A5 this is wired up to PM8916 GPIO2, which is then configured with a special function (NFC_CLK_REQ or BB_CLK2_REQ). Enabling the rpmcc RPM_SMD_BB_CLK2_PIN clock will then instruct PM8916 to automatically enable the clock whenever the NFC chip requests it. The advantage is that the clock is only enabled when needed and we don't need to manage it ourselves from the NFC driver. Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com> Link: https://lore.kernel.org/r/20240601115321.25314-3-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06arm64: dts: qcom: msm8916-samsung-gprimeltecan: Add NFCJoe Mason2-0/+55
The Samsung Galaxy Grand Prime CAN has a Samsung S3FWRN5 NFC chip that works quite well with the s3fwrn5 driver in the Linux NFC subsystem. The clock setup for the NFC chip is a bit special (although this seems to be a common approach used for Qualcomm devices with NFC): The NFC chip has an output GPIO that is asserted whenever the clock is needed to function properly. On the A3/A5 this is wired up to PM8916 GPIO2, which is then configured with a special function (NFC_CLK_REQ or BB_CLK2_REQ). Enabling the rpmcc RPM_SMD_BB_CLK2_PIN clock will then instruct PM8916 to automatically enable the clock whenever the NFC chip requests it. The advantage is that the clock is only enabled when needed and we don't need to manage it ourselves from the NFC driver. Signed-off-by: Joe Mason <buddyjojo06@outlook.com> [Stephan: Put NFC pinctrl into common dtsi to share it with other variants] Signed-off-by: Stephan Gerhold <stephan@gerhold.net> [Raymond: Use interrupts-extended. Keep &blsp_i2c6 enabled by default] Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com> Link: https://lore.kernel.org/r/20240601115321.25314-2-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06arm64: dts: qcom: x1e80100: Disable the SMB2360 4th instance by defaultAbel Vesa2-0/+6
The CRD board doesn't have the 4th SMB2360 PMIC populated while the QCP does. So enable it on QCP only. This fixes the warning for the missing PMIC on CRD as well. Fixes: 2559e61e7ef4 ("arm64: dts: qcom: x1e80100-pmics: Add the missing PMICs") Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240603-x1e80100-dts-pmics-drop-4th-smb2360-from-crd-v2-1-fb63973cc07d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06arm64: dts: qcom: sc7280: Disable SuperSpeed instances in park modeKrishna Kurapati1-0/+1
On SC7280, in host mode, it is observed that stressing out controller results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instances in park mode for SC7280 to mitigate this issue. Reported-by: Doug Anderson <dianders@google.com> Cc: stable@vger.kernel.org Fixes: bb9efa59c665 ("arm64: dts: qcom: sc7280: Add USB related nodes") Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240604060659.1449278-3-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06arm64: dts: qcom: sc7180: Disable SuperSpeed instances in park modeKrishna Kurapati1-0/+1
On SC7180, in host mode, it is observed that stressing out controller results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instances in park mode for SC7180 to mitigate this issue. Reported-by: Doug Anderson <dianders@google.com> Cc: stable@vger.kernel.org Fixes: 0b766e7fe5a2 ("arm64: dts: qcom: sc7180: Add USB related nodes") Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240604060659.1449278-2-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06arm64: dts: qcom: qrb4210-rb2: make L9A always-onDmitry Baryshkov1-0/+2
The L9A regulator is used to further control voltage regulators on the board. It can be used to disable VBAT_mains, 1.8V, 3.3V, 5V rails). Make sure that is stays always on to prevent undervolting of these volage rails. Fixes: 8d58a8c0d930 ("arm64: dts: qcom: Add base qrb4210-rb2 board dts") Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240605-rb2-l9a-aon-v2-1-0d493d0d107c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06arm64: dts: qcom: qrb4210-rb2: switch I2C2 to i2c-gpioDmitry Baryshkov1-1/+12
On the Qualcomm RB2 platform the I2C bus connected to the LT9611UXC bridge under some circumstances can go into a state when all transfers timeout. This causes both issues with fetching of EDID and with updating of the bridge's firmware. While we are debugging the issue, switch corresponding I2C bus to use i2c-gpio driver. While using i2c-gpio no communication issues are observed. This patch is asusmed to be a temporary fix, so it is implemented in a non-intrusive manner to simply reverting it later. Fixes: f7b01e07e89c ("arm64: dts: qcom: qrb4210-rb2: Enable display out") Cc: stable@vger.kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Link: https://lore.kernel.org/r/20240605-rb12-i2c2g-pio-v2-2-946f5d6b6948@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06arm64: dts: qcom: qrb2210-rb1: switch I2C2 to i2c-gpioDmitry Baryshkov1-1/+12
On the Qualcomm RB1 platform the I2C bus connected to the LT9611UXC bridge under some circumstances can go into a state when all transfers timeout. This causes both issues with fetching of EDID and with updating of the bridge's firmware. While we are debugging the issue, switch corresponding I2C bus to use i2c-gpio driver. While using i2c-gpio no communication issues are observed. This patch is asusmed to be a temporary fix, so it is implemented in a non-intrusive manner to simply reverting it later. Fixes: 616eda24edd4 ("arm64: dts: qcom: qrb2210-rb1: Set up HDMI") Cc: stable@vger.kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Link: https://lore.kernel.org/r/20240605-rb12-i2c2g-pio-v2-1-946f5d6b6948@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06arm64: dts: qcom: sm8650-hdk: allow more IOMMU SID for the first QUP instanceNeil Armstrong1-0/+2
When triggering I2S SE DMA transfers on the 6th Serial Element, we get some timeouts and finally a fatal SMMU crash because the I2C6 lines are shared with the secure firmware in order to handle the SMB1396 charger from the secure side. In order to make thing work flawlessly we need to allow more SIDs while running our SE DMA transfers, thus add the 0x3 mark to allow the 0xa0 SID to trigger while we trigger an 0xa3 SID from Linux. This crash doesn't happen on the QRD platform since the SE6 is configured differently, with FIFO mode disabled, thus GPI DMA is used and we cannot exercise SE DMA on this interface. The crash only happens when large tranfers occurs (>32 bytes) since the driver is designed to use the SE DMA in this case, and there's no way to mark the SE DMA as disabled or mark the GPI DMA as preferred since the FIFO/SE DMA will be used is FIFO is not disabled. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Fixes: 01061441029e ("arm64: dts: qcom: sm8650: add support for the SM8650-HDK board") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240605-topic-sm8650-upstream-hdk-iommu-fix-v1-1-9fd7233725fa@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-06arm64: dts: qcom: use defines for interruptsKrzysztof Kozlowski4-16/+16
Replace hard-coded interrupt parts (GIC, flags) with standard defines for readability. No changes in resulting DTBs. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240605154605.149051-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-04arm64: dts: qcom: msm8994: Use mboxes properties for APCSLuca Weiss1-3/+3
Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240424-apcs-mboxes-v1-7-6556c47cb501@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-04arm64: dts: qcom: msm8976: Use mboxes properties for APCSLuca Weiss1-4/+4
Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240424-apcs-mboxes-v1-6-6556c47cb501@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-04arm64: dts: qcom: msm8953: Use mboxes properties for APCSLuca Weiss1-5/+5
Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240424-apcs-mboxes-v1-5-6556c47cb501@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-04arm64: dts: qcom: msm8939: Use mboxes properties for APCSLuca Weiss1-2/+2
Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240424-apcs-mboxes-v1-4-6556c47cb501@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-04arm64: dts: qcom: msm8916: Use mboxes properties for APCSLuca Weiss1-5/+5
Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240424-apcs-mboxes-v1-3-6556c47cb501@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-04arm64: dts: qcom: sa8775p: Correct IRQ number of EL2 non-secure physical timerCong Zhang1-1/+1
The INTID of EL2 non-secure physical timer is 26. In linux, the IRQ number has a fixed 16 offset for PPIs. Therefore, the linux IRQ number of EL2 non-secure physical timer should be 10 (26 - 16). Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride") Signed-off-by: Cong Zhang <quic_congzhan@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20240604085929.49227-1-quic_congzhan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-02arm64: dts: qcom: ipq8074: fix GCC node nameDmitry Baryshkov1-1/+1
Device nodes should have generic names. Use 'clock-controller@' as a GCC node name instead of a non-generic 'gcc@'. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-14-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-02arm64: dts: qcom: ipq6018: fix GCC node nameDmitry Baryshkov1-1/+1
Device nodes should have generic names. Use 'clock-controller@' as a GCC node name instead of a non-generic 'gcc@'. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-13-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-02arm64: dts: qcom: ipq9574: drop #power-domain-cells property of GCCDmitry Baryshkov1-1/+0
On IPQ9574 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-12-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-02arm64: dts: qcom: ipq5332: drop #power-domain-cells property of GCCDmitry Baryshkov1-1/+0
On IPQ5332 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-11-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-02arm64: dts: qcom: ipq5018: drop #power-domain-cells property of GCCDmitry Baryshkov1-1/+0
On IPQ5018 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-10-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-02arm64: dts: qcom: sm8650-hdk: remove redundant propertiesDmitry Baryshkov1-15/+0
The commit 65931e59e039 ("arm64: dts: qcom: sm8650: move USB graph to the SoC dtsi") and commit fbb22a182267 ("arm64: dts: qcom: sm8650: move PHY's orientation-switch to SoC dtsi") have moved some of the properties from the board DT files to the sm8650.dtsi. As the patch for sm8650 HDK predates those commits, it still had those properties inside. Drop these duplicate proerties from the sm8650-hdk.dts. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240530-sm8650-hdk-redundant-v1-1-c39c2ae65f3b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-02arm64: dts: qcom: sm7225-fairphone-fp4: Enable USB role switchingLuca Weiss3-1/+108
Configure the Type-C and VBUS regulator on PM7250B and wire it up to the USB PHY, so that USB role and orientation switching works. For now USB Power Delivery properties are skipped / disabled, so that the (presumably) bootloader-configured charger doesn't get messed with and we can charge the phone with at least some amount of power. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240530-fp4-tcpm-v3-3-612d4bbd5e09@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-02arm64: dts: qcom: pm7250b: Add a TCPM descriptionLuca Weiss1-0/+40
Type-C port management functionality lives inside of the PMIC block on pm7250b. The Type-C port management logic controls orientation detection, vbus/vconn sense and to send/receive Type-C Power Domain messages. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240530-fp4-tcpm-v3-2-612d4bbd5e09@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-02arm64: dts: qcom: pm7250b: Add node for PMIC VBUS boosterLuca Weiss1-0/+6
Add the required DTS node for the USB VBUS output regulator, which is available on PM7250B. This will provide the VBUS source to connected peripherals. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240530-fp4-tcpm-v3-1-612d4bbd5e09@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-02arm64: dts: qcom: x1e80100: Describe the PCIe 6a resourcesAbel Vesa2-0/+104
On both the CRD and QCP, on PCIe 6a sits the NVMe. Add the 3.3V gpio-controlled regulator and the clkreq, perst and wake gpios as resources for the PCIe 6a. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240530-x1e80100-dts-pcie6a-v1-3-ee17a9939ba5@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-02arm64: dts: qcom: x1e80100-qcp: Fix the PHY regulator for PCIe 6aAbel Vesa1-1/+1
The actual PHY regulator is L1d instead of L3j, so fix it accordingly. Fixes: f9a9c11471da ("arm64: dts: qcom: x1e80100-qcp: Enable more support") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: stable@vger.kernel.org # 6.9 Link: https://lore.kernel.org/r/20240530-x1e80100-dts-pcie6a-v1-2-ee17a9939ba5@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-02arm64: dts: qcom: x1e80100-crd: Fix the PHY regulator for PCIe 6aAbel Vesa1-1/+1
The actual PHY regulator is L1d instead of L3j, so fix it accordingly. Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: stable@vger.kernel.org # 6.9 Link: https://lore.kernel.org/r/20240530-x1e80100-dts-pcie6a-v1-1-ee17a9939ba5@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-02arm64: dts: qcom: x1e80100-qcp: Fix USB PHYs regulatorsAbel Vesa1-3/+12
The 1.2v HS PHY shared regulator is actually LDO2 from PM8550ve id J. Also add the missing supplies to QMP PHYs. Fixes: f9a9c11471da ("arm64: dts: qcom: x1e80100-qcp: Enable more support") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: stable@vger.kernel.org # 6.9 Link: https://lore.kernel.org/r/20240530-x1e80100-dts-fix-usb-phy-supplies-v1-2-6eb72a546227@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-01arm64: dts: qcom: x1e80100-crd: Fix USB PHYs regulatorsAbel Vesa1-3/+12
The 1.2v HS PHY shared regulator is actually LDO2 from PM8550ve id J. Also add the missing supplies to QMP PHYs. Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: stable@vger.kernel.org # 6.9 Link: https://lore.kernel.org/r/20240530-x1e80100-dts-fix-usb-phy-supplies-v1-1-6eb72a546227@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-02 18:44:22 +0300