summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/qcom
AgeCommit message (Collapse)AuthorFilesLines
2024-10-22arm64: dts: qcom: sa8775p: Add GPI configurationViken Dadhaniya1-0/+246
I2C and SPI geni driver also supports the GSI node based on client requirements. Currently, in the DTSI, the GSI mode configuration is not added. Therefore, add GPI DT nodes for QUPV_0/1/2/3 for I2C and SPI for the SA8775. Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> Link: https://lore.kernel.org/r/20241021102815.12079-1-quic_vdadhani@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-16arm64: dts: qcom: x1e80100: Resize GIC Redistributor register regionSibi Sankar1-1/+1
Resize the GICR register region as it currently seeps into the CPU Control Processor mailbox RX region. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Link: https://lore.kernel.org/r/20240612124056.39230-4-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-16arm64: dts: qcom: x1e80100: Fix PCIe 6a lanes descriptionAbel Vesa1-3/+6
Fix the description and compatible for PCIe 6a, as it is in fact a 4-lanes controller and PHY, but it can also be used in 2-lanes mode. For 4-lanes mode, it uses the lanes provided by PCIe 6b. For 2-lanes mode, PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. The number of lanes in which the PHY should be configured depends on a TCSR register value on each individual board. Cc: stable+noautosel@kernel.org # Depends on pcie-qcom 16.0 GT/s support Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241009-x1e80100-dts-fixes-pcie6a-v3-1-14a1163e691b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-16arm64: dts: qcom: x1e80100: rename vph-pwr regulator nodesJohan Hovold4-44/+44
Rename the x1e80100 vph-pwr regulator nodes to use "regulator" as a prefix for consistency with the other fixed regulators. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241015122601.16127-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: sa8775p: extend the register range for UFS ICEBartosz Golaszewski1-1/+1
The full register range for ICE on sa8775p is 0x18000 so update the crypto node. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20241007-wrapped-keys-dts-v8-3-05ee041f2fc1@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: sm8550: extend the register range for UFS ICEBartosz Golaszewski1-1/+2
The full register range for ICE on sm8550 is 0x18000 so update the crypto node. Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> Co-developed-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20241007-wrapped-keys-dts-v8-2-05ee041f2fc1@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: sm8650: extend the register range for UFS ICEBartosz Golaszewski1-1/+1
The full register range for ICE on sm8650 is 0x18000 so update the crypto node. Reviewed-by: Om Prakash Singh <quic_omprsing@quicinc.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> Co-developed-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20241007-wrapped-keys-dts-v8-1-05ee041f2fc1@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: sa8775p: Populate additional UART DT nodesViken Dadhaniya1-0/+231
Currently, UART configuration is populated for only a few SEs (Serial Engines) in the sa8775p DTSI file. Since every SE can support the UART protocol, usecase or client should have the flexibility to enable required SE for UART depending on the specific board version. Hence, populate UART configurations for the remaining SEs in the sa8775p SoC. Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> Link: https://lore.kernel.org/r/20241007091407.13798-1-quic_vdadhani@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: sm8450 fix PIPE clock specification for pcie1Dmitry Baryshkov1-1/+1
For historical reasons on SM8450 the second PCIe host (pcie1) also keeps a reference to the PIPE clock coming from the PHY. Commit e76862840660 ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc") has updated the PHY to use #clock-cells = <1>, making just <&pcie1_phy> clock specification invalid. Update corresponding clock entry in the PCIe1 host node. /soc@0/pcie@1c08000: Failed to get clk index: 2 ret: -22 qcom-pcie 1c08000.pcie: Failed to get clocks qcom-pcie 1c08000.pcie: probe with driver qcom-pcie failed with error -22 Fixes: e76862840660 ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241006-fix-sm8450-pcie1-v1-1-4f227c9082ed@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: x1e80100-t14s: add another trackpad supportSrinivas Kandagatla1-4/+13
Trackpad HID device on T14s could be found on two possible slave addresses (hid@15 and hid@2c) on i2c0 instance. With the current state of DT boot, there is no way to patch the device tree at runtime during boot. This, however results in non-functional trackpad on Product Models 21N2ZC5PUS which have trackpad on hid@2c slave address. This patch adds hid@2c device along with hid@15 to get it working on both the variants. This should work as i2c-hid driver will stop probing the device if there is nothing on the slave address, we can actually keep both devices enabled in DT, and i2c-hid driver will only probe the existing one. The only problem is that we cannot setup pinctrl in both device nodes, as two devices with the same pinctrl will cause pin conflict that makes the second device fail to probe. Let's move the pinctrl state up to parent node along with the parent pinctrl to solve this problem. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241004130849.2944-1-srinivas.kandagatla@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: Add support for X1-based Dell XPS 13 9345Aleksandrs Vinarskis2-0/+864
Initial support for Dell XPS 9345 13" 2024 (Codenamed 'Tributo') based on X1E80100. Working: * Touchpad * Keyboard (only post suspend&resume, i2c-hid patch required [1]) * Touchscreen * eDP (low-res IPS, OLED) with brightness control * NVME * USB Type-C ports in USB2/USB3 (one orientation) * WiFi * GPU/aDSP/cDSP firmware loading (requires binaries from Windows) * Lid switch * Sleep/suspend, nothing visibly broken on resume Not working: * Speakers (WIP, pin guessing, x4 WSA8845) * Microphones (WIP, pin guessing, dual array) * Fingerprint Reader (WIP, USB MP with ptn3222) * USB as DP/USB3 (WIP, PS8830 based) * Camera (Likely OV01A10) * EC over i2c Should be working, but cannot be tested due to lack of hw: * higher res IPS panel [1] https://lore.kernel.org/all/20240925100303.9112-1-alex.vinarskis@gmail.com/ Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Tested-by: Stefan Schmidt <stefan.schmidt@linaro.org> Link: https://lore.kernel.org/r/20241003211139.9296-4-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: x1e78100-t14s: enable otg on usb-c portsJonathan Marek1-8/+0
The 2 USB-C ports on x1e78100-t14s are OTG-capable, remove the dr_mode override to enable OTG. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241011231624.30628-3-jonathan@marek.ca Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: x1e80100-crd: enable otg on usb portsJonathan Marek1-12/+0
The 3 USB ports on x1e80100-crd are OTG-capable, remove the dr_mode override to enable OTG. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241011231624.30628-2-jonathan@marek.ca Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: x1e80100: enable OTG on USB-C controllersJonathan Marek1-0/+6
These 3 controllers support OTG and the driver requires the usb-role-switch property to enable OTG. Add the property to enable OTG by default. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241011231624.30628-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: x1e80100: Add Broadcast_AND region in LLCC blockAbel Vesa1-2/+4
Add missing Broadcast_AND region to the LLCC block for x1e80100, as the LLCC version on this platform is 4.1 and it provides the region. This also fixes the following error caused by the missing region: [ 3.797768] qcom-llcc 25000000.system-cache-controller: error -EINVAL: invalid resource (null) This error started showing up only after the new regmap region called Broadcast_AND that has been added to the llcc-qcom driver. Cc: stable@vger.kernel.org # 6.11: 055afc34fd21: soc: qcom: llcc: Add regmap for Broadcast_AND region Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241014-x1e80100-dts-llcc-add-broadcastand_region-v2-1-5ee6ac128627@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: x1e80100-vivobook-s15: Drop orientation-switch from USB ↵Abel Vesa1-4/+0
SS[0-1] QMP PHYs The orientation-switch is already set in the x1e80100 SoC dtsi, so drop from Vivobook S15 dts. Fixes: d0e2f8f62dff ("arm64: dts: qcom: Add device tree for ASUS Vivobook S 15") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241014-x1e80100-dts-drop-orientation-switch-v1-2-26afa6d4afd9@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: x1e80100-slim7x: Drop orientation-switch from USB SS[0-1] ↵Abel Vesa1-4/+0
QMP PHYs The orientation-switch is already set in the x1e80100 SoC dtsi, so drop from Slim 7X dts. Fixes: 45247fe17db2 ("arm64: dts: qcom: x1e80100: add Lenovo Thinkpad Yoga slim 7x devicetree") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241014-x1e80100-dts-drop-orientation-switch-v1-1-26afa6d4afd9@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: Drop undocumented domain "idle-state-name"Rob Herring (Arm)2-5/+0
"idle-state-name" is not a valid property for "domain-idle-state" binding, so drop it. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20241014161631.1527918-2-robh@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: sc7280: Add 0x81 Adreno speed binEugene Lepshy1-4/+4
A642L (speedbin 0x81) uses index 4, so this commit sets the fourth bit for A642L supported opps. Signed-off-by: Eugene Lepshy <fekz115@gmail.com> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20241014194825.44406-2-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-15arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIeJohan Hovold1-2/+4
The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS). Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. This specifically allows NVMe and Wi-Fi interrupts to be processed on all cores (and not just on CPU0). Note that using the GIC ITS on x1e80100 will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. Consequently, notifications about (correctable) errors may now be logged for errors that previously went unnoticed. Also note that PCIe5 (and PCIe3) can currently only be used with the internal MSI controller due to a platform (firmware) limitation. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241009161715.14994-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-08arm64: dts: qcom: qcs6490-rb3gen2: Enable PWR/VOL keysKonrad Dybcio1-0/+35
RB3Gen2 has three tiny buttons located under the blue USB-A ports. They're all connected through the various PMICs and are used for volume and power. Describe them. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241004-rb3gen2-pwr-vol-keys-v1-1-4b1859c7cc4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-08arm64: dts: qcom: qcs6490-rb3gen2: Specify i2c1 clock frequencyBjorn Andersson1-0/+1
Per the binding, omitting the clock frequency from a Geni I2C controller node defaults the bus to 100Khz. But at least in Linux, a friendly info print highlights the lack of explicitly defined frequency in the DeviceTree. Specify the frequency, to give it an explicit value, and to silence the log print in Linux. Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241004-i2c1-frequency-v1-1-77a359015d54@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-07arm64: dts: qcom: sda660-ifc6560: enable mDSP and WiFi devicesDmitry Baryshkov1-0/+22
Enable the onboard WiFi device present on the Inforce IFC6560 SBC. Pretty much like MSM8998 this device also doesn't generate the MSA_READY_IND indication. For the reference: ath10k_snoc 18800000.wifi: qmi chip_id 0x30214 chip_family 0x4001 board_id 0xff soc_id 0x40050000 ath10k_snoc 18800000.wifi: qmi fw_version 0x101d01da fw_build_timestamp 2018-07-26 21:42 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.1.0.1.c2-00474-QCAHLSWMTPLZ-1 ath10k_snoc 18800000.wifi: qmi not waiting for msa_ready indicator ath10k_snoc 18800000.wifi: wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 ath10k_snoc 18800000.wifi: kconfig debug 1 debugfs 0 tracing 0 dfs 0 testmode 0 ath10k_snoc 18800000.wifi: firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 ath10k_snoc 18800000.wifi: htt-ver 3.54 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 ath10k_snoc 18800000.wifi: invalid MAC address; choosing random Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-7-e316055142f8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-07arm64: dts: qcom: sdm630: add WiFI device nodeDmitry Baryshkov1-0/+27
Add device node for the WiFi device being a part of the integrated SDM660 / SDM630 platforms. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-6-e316055142f8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-07arm64: dts: qcom: sdm630: enable A2NOC and LPASS SMMUDmitry Baryshkov1-4/+0
Now as the arm-smmu-qcom driver gained workarounds for the A2NOC and LPASS SMMU devices, enable those two devices. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-5-e316055142f8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-07arm64: dts: qcom: sda660-ifc6560: fix l10a voltage rangesDmitry Baryshkov1-1/+1
L10A, being a fixed regulator, should have min_voltage = max_voltage, otherwise fixed rulator fails to probe. Fix the max_voltage range to be equal to minimum. Fixes: 4edbcf264fe2 ("arm64: dts: qcom: sda660-ifc6560: document missing USB PHY supplies") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-4-e316055142f8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-07arm64: dts: qcom: sda660-ifc6560: enable GPUDmitry Baryshkov2-0/+12
Enable Adreno GPU on the Inforce IFC6560 SBC. It requires the Zap shader binary that was provided by the vendor. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-3-e316055142f8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-07arm64: dts: qcom: sdm630: enable GPU SMMU and GPUCCDmitry Baryshkov1-3/+0
Now as the arm-smmu-qcom driver gained workarounds for the Adreno SMMU, it becomes possible to safely enable GPU on the devices. Enable GPU SMMU and GPU clock controller. GPU should be enabled for target devices that have ZAP shader blob. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-2-e316055142f8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: qcm6490-fairphone-fp5: Add thermistor for UFS/RAMLuca Weiss1-0/+40
Configure the ADC and thermal zone for the thermistor next to the UFS+RAM chip which is connected to GPIO_12 of PM7250B. It is used to measure the temperature of that area of the PCB. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20241002-fp5-ufs-therm-v1-1-1d2d8c1f08b5@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sm6350: Fix GPU frequencies missing on some speedbinsLuca Weiss1-7/+7
Make sure the GPU frequencies are marked as supported for the respective speedbins according to downstream msm-4.19 kernel: * 850 MHz: Speedbins 0 + 180 * 800 MHz: Speedbins 0 + 180 + 169 * 650 MHz: Speedbins 0 + 180 + 169 + 138 * 565 MHz: Speedbins 0 + 180 + 169 + 138 + 120 * 430 MHz: Speedbins 0 + 180 + 169 + 138 + 120 * 355 MHz: Speedbins 0 + 180 + 169 + 138 + 120 * 253 MHz: Speedbins 0 + 180 + 169 + 138 + 120 Fixes: bd9b76750280 ("arm64: dts: qcom: sm6350: Add GPU nodes") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20241002-sm6350-gpu-speedbin-fix-v1-1-8a5d90c5097d@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sc8280xp: Add Microsoft Surface Pro 9 5GJérôme de Bretagne2-0/+1033
Add an initial devicetree for the Microsoft Surface Pro 9 5G, based on SC8280XP. It enables the support for Wi-Fi, NVMe, the two USB Type-C ports, Bluetooth, 5G cellular modem, audio output (via Bluetooth headsets or USB audio), external display via DisplayPort over Type-C (only the bottom USB Type-C port is working so far), charging, the Surface Aggregator Module (SAM) to get keyboard and touchpad working with Surface Type Cover accessories. Some key features not supported yet: - built-in display (but software fallback is working with efifb when blacklisting the msm module) - built-in display touchscreen - external display with the top USB Type-C port - speakers and microphones - physical volume up and down keys - LID switch detection This devicetree is based on the other SC8280XP ones, for the Lenovo ThinkPad X13s and the Qualcomm CRD. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Link: https://lore.kernel.org/r/20240908223505.21011-6-jerome.debretagne@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sc8280xp: Add uart18Jérôme de Bretagne1-0/+48
Add the node describing uart18 for sc8280xp devices. Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Link: https://lore.kernel.org/r/20240908223505.21011-5-jerome.debretagne@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: minor whitespace cleanupKrzysztof Kozlowski6-6/+6
The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240905-dts-cleanup-v1-4-f4c5f7b2c8c2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: drop underscore in node namesKrzysztof Kozlowski3-3/+3
Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Functional impact checked with comparing before/after DTBs with dtx_diff and fdtdump. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240905-dts-cleanup-v1-3-f4c5f7b2c8c2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: x1e80100-romulus: Set up USB Multiport controllerKonrad Dybcio1-2/+57
The USB MP controller is wired up to the USB-A port on the left side and to the Surface Connector on the right side. Configure it. While at it, remove a stray double \n. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240902-topic-sl7_updates-v1-2-3ee667e6652d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: x1e80100-romulus: Add lid switchKonrad Dybcio1-0/+23
One of the best parts of having a laptop is being able to close the lid and go on with your day. Enable this feature by defining the lid switch. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240902-topic-sl7_updates-v1-1-3ee667e6652d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sc7280: Fix PMU nodes for Cortex A55 and A78Danila Tikhonov1-2/+7
The SC7280, SM7325, and QCM6490 platforms feature an 8-core setup consisting of: - 1x Kryo 670 Prime (Cortex-A78) / Kryo 670 Gold Plus (Cortex-A78) - 3x Kryo 670 Gold (Cortex-A78) - 4x Kryo 670 Silver (Cortex-A55) (The CPU cores in the SC7280 are simply called Kryo, but are nevertheless based on the same Cortex A78 and A55). Use the correct compatibility. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Link: https://lore.kernel.org/r/20240818192905.120477-1-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: x1e80100: Add debug uart to Lenovo Yoga Slim 7xMaya Matuszczyk1-0/+13
This commit enables the debug UART found on the motherboard under the SSD Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com> Link: https://lore.kernel.org/r/20241004192436.16195-2-maccraft123mc@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: x1e80100: describe tcsr download mode registerJohan Hovold1-0/+1
Describe the TCSR download mode register to enable download mode control. This specifically allows the OS to disable download mode in case the boot firmware has left it enabled to avoid entering the crash dump mode after a hypervisor reset by default. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241002100122.18809-3-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: x1e80100: fix PCIe5 PHY clocksJohan Hovold1-3/+5
Add the missing clkref enable and pipediv2 clocks to the PCIe5 PHY. Fixes: 62ab23e15508 ("arm64: dts: qcom: x1e80100: add PCIe5 nodes") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240916082307.29393-4-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: x1e80100: fix PCIe4 and PCIe6a PHY clocksJohan Hovold1-6/+10
Add the missing clkref enable and pipediv2 clocks to the PCIe4 and PCIe6a PHYs. Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") Cc: stable@vger.kernel.org # 6.9 Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240916082307.29393-3-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: qcs6460-rb3gen2: enable venus nodeVedang Nagar1-0/+4
Enable the venus node on Qualcomm Rb3gen2 so that the video decoder will start working. Signed-off-by: Vedang Nagar <quic_vnagar@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240917-venus_rb3_gen2-v1-1-8fea70733592@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio1-0/+2
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-11-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sm8450: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio1-0/+1
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-10-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio1-0/+1
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-9-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio1-0/+1
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-8-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio1-0/+1
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sm7225-fairphone-fp4 Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-7-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio1-0/+1
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-6-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio1-0/+1
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-5-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio1-0/+1
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-4-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-28 08:21:39 +0300