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2025-01-07arm64: dts: qcom: sm8350: Disable USB U1/U2 entryKrishna Kurapati1-0/+4
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-2-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8750: Add MTP and QRD boardsMelody Olvera3-0/+1588
Add MTP and QRD dts files for SM8750 describing board clocks, regulators, gpio keys, etc. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241204-sm8750_master_dt-v3-6-4d5a8269950b@quicinc.com [bjorn: Polished subject] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8750: Add pmic dtsiMelody Olvera1-0/+188
Add pmic dtsi file for SM8750 SoC describing the pmics and their thermal zones. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241204-sm8750_master_dt-v3-5-4d5a8269950b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: Add base SM8750 dtsiMelody Olvera1-0/+2907
Add the base dtsi for the SM8750 SoC describing the CPUs, GCC and RPMHCC clock controllers, geni UART, interrupt controller, TLMM, reserved memory, interconnects, and SMMU. Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Co-developed-by: Jishnu Prakash <quic_jprakash@quicinc.com> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241204-sm8750_master_dt-v3-4-4d5a8269950b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: Add PMIH0108 PMICMelody Olvera1-0/+68
Add descriptions of PMIH0108 PMIC used on SM8750 platforms. Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241204-sm8750_master_dt-v3-3-4d5a8269950b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: Add PMD8028 PMICMelody Olvera1-0/+62
Add descriptions of PMD8028 PMIC used on SM8750 platforms. Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241204-sm8750_master_dt-v3-2-4d5a8269950b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: x1e80100: Fix interconnect tags for SDHC nodesAbel Vesa1-4/+8
The CPU-to-SDHC interconnect path for the SDHC_2 needs to have the active-only tags. The tags are missing entirely on for the SDHC_4 controller interconnect paths. Fix all tags for both controllers. Fixes: ffb21c1e19b1 ("arm64: dts: qcom: x1e80100: Describe the SDHC controllers") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241227-b4-x1e80100-qcp-sdhc-fixes-v1-1-cd971f7f0955@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: qrb4210-rb2: add HDMI audio playback supportAlexey Klimov1-0/+59
Add sound node and dsp-related piece to enable HDMI audio playback support on Qualcomm QRB4210 RB2 board. That is the only sound output supported for now. The audio playback is verified using the following commands: amixer -c0 cset iface=MIXER,name='SEC_MI2S_RX Audio Mixer MultiMedia1' 1 aplay -D hw:0,0 /usr/share/sounds/alsa/Front_Center.wav Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241112025306.712122-5-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm4250: add LPASS LPI pin controllerAlexey Klimov1-0/+39
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node required for audio subsystem on Qualcomm QRB4210 RB2. QRB4210 is based on sm4250 which has a slightly different lpass pin controller comparing to sm6115. While at this, also add description of lpi_i2s2 pins (active state) required for audio playback via HDMI. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241112025306.712122-4-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm6115: add LPASS LPI pin controllerAlexey Klimov1-0/+15
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node required for audio subsystem on Qualcomm QRB4210 RB2. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241112025306.712122-3-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm6115: add apr and its servicesAlexey Klimov1-0/+72
Add apr (asynchronous packet router) node and its associated services required to enable audio on QRB4210 RB2 platform. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241112025306.712122-2-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm8650: Fix CDSP context banks unit addressesKrzysztof Kozlowski1-3/+3
There is a mismatch between 'reg' property and unit address for last there CDSP compute context banks. Current values were taken as-is from downstream source. Considering that 'reg' is used by Linux driver as SID of context bank and that least significant bytes of IOMMU value match the 'reg', assume the unit-address is wrong and needs fixing. This also won't have any practical impact, except adhering to Devicetree spec. Fixes: dae8cdb0a9e1 ("arm64: dts: qcom: sm8650: Add three missing fastrpc-compute-cb nodes") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241104144204.114279-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: q[dr]u1000: move board clocks to qdu1000.dtsi fileDmitry Baryshkov3-28/+14
The QDU1000 and QRU1000 devices define XO and clocks completely in the board files, despite qdu1000.dtsi file referencing them directly. Follow the example of other platforms and move clock definitions to the qdu1000.dtsi file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-21-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sdm670: move board clocks to sdm670.dtsi fileDmitry Baryshkov2-14/+14
The SDM670 devices define XO and clocks completely in the board files, despite sdm670.dtsi file referencing them directly. Follow the example of other platforms and move clock definitions to the sdm670.dtsi file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-20-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sc8180x: drop extra XO clock frequenciesDmitry Baryshkov2-8/+0
sc8180x.dtsi already defines 38.4 MHz clock frequency for the XO clock. Drop duplicate overrides from Primus and Lenovo Flex 5G DT files. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-19-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: x1e80100: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The X1E80100 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-18-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm8650: correct sleep clock frequencyDmitry Baryshkov3-3/+3
The SM8650 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 6fbdb3c1fac7 ("arm64: dts: qcom: sm8650: add initial SM8650 MTP dts") Fixes: a834911d50c1 ("arm64: dts: qcom: sm8650: add initial SM8650 QRD dts") Fixes: 01061441029e ("arm64: dts: qcom: sm8650: add support for the SM8650-HDK board") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-17-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm8550: correct sleep clock frequencyDmitry Baryshkov6-6/+6
The SM8550 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 0b12da4e28d8 ("arm64: dts: qcom: add base AIM300 dtsi") Fixes: b5e25ded2721 ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board") Fixes: 71342fb91eae ("arm64: dts: qcom: Add base SM8550 MTP dts") Fixes: d228efe88469 ("arm64: dts: qcom: sm8550-qrd: add QRD8550") Fixes: ba2c082a401f ("arm64: dts: qcom: sm8550: Add support for Samsung Galaxy Z Fold5") Fixes: 39c596304e44 ("arm64: dts: qcom: Add SM8550 Xperia 1 V") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-16-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm8450: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The SM8450 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-15-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm8350: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The SM8350 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-14-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm8250: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The SM8250 platform uses PM8150 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9ff8b0591fcf ("arm64: dts: qcom: sm8250: use the right clock-freqency for sleep-clk") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-13-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm6375: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The SM6375 platform uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-12-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm6125: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The SM6125 platform uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-11-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm4450: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The SM4450 platform uses PM4450 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 7a1fd03e7410 ("arm64: dts: qcom: Adds base SM4450 DTSI") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-10-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sdx75: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The SDX75 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9181bb939984 ("arm64: dts: qcom: Add SDX75 platform and IDP board support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-9-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sc7280: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The SC7280 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 7a1f4e7f740d ("arm64: dts: qcom: sc7280: Add basic dts/dtsi files for sc7280 soc") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-8-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sar2130p: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The SAR2130P platform uses PM8150 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: be9115bfe5bf ("arm64: dts: qcom: sar2130p: add support for SAR2130P") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-7-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: qrb4210-rb2: correct sleep clock frequencyDmitry Baryshkov1-1/+1
Qualcomm RB2 board uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 8d58a8c0d930 ("arm64: dts: qcom: Add base qrb4210-rb2 board dts") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-6-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: q[dr]u1000: correct sleep clock frequencyDmitry Baryshkov2-2/+2
The Q[DR]U1000 platforms use PM8150 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: d1f2cfe2f669 ("arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-5-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: qcs404: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The QCS40x platforms use PMS405 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9181bb939984 ("arm64: dts: qcom: Add SDX75 platform and IDP board support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-4-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: msm8994: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The MSM8994 platform uses PM8994/6 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: feeaf56ac78d ("arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-3-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: msm8939: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The MSM8939 platform uses PM8916 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 61550c6c156c ("arm64: dts: qcom: Add msm8939 SoC") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-2-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: msm8916: correct sleep clock frequencyDmitry Baryshkov1-1/+1
The MSM8916 platform uses PM8916 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: f4fb6aeafaaa ("arm64: dts: qcom: msm8916: Add fixed rate on-board oscillators") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-1-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm8650: correct MDSS interconnectsDmitry Baryshkov1-4/+1
SM8650 lists two interconnects for the display subsystem, mdp0-mem (between MDP and LLCC) and mdp1-mem (between LLCC and EBI, memory). The second interconnect is a misuse. mdpN-mem paths should be used for several outboud MDP interconnects rather than the path between LLCC and memory. This kind of misuse can result in bandwidth underflows, possibly degrading picture quality as the required memory bandwidth is divided between all mdpN-mem paths (and LLCC-EBI should not be a part of such division). Drop the second path and use direct MDP-EBI path for mdp0-mem until we support separate MDP-LLCC and LLCC-EBI paths. Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Cc: stable@kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241026-fix-sm8x50-mdp-icc-v2-2-fd8ddf755acc@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm8550: correct MDSS interconnectsDmitry Baryshkov1-3/+2
SM8550 lists two interconnects for the display subsystem, mdp0-mem (between MDP and LLCC) and mdp1-mem (between LLCC and EBI, memory). The second interconnect is a misuse. mdpN-mem paths should be used for several outboud MDP interconnects rather than the path between LLCC and memory. This kind of misuse can result in bandwidth underflows, possibly degrading picture quality as the required memory bandwidth is divided between all mdpN-mem paths (and LLCC-EBI should not be a part of such division). Drop the second path and use direct MDP-EBI path for mdp0-mem until we support separate MDP-LLCC and LLCC-EBI paths. Fixes: d7da51db5b81 ("arm64: dts: qcom: sm8550: add display hardware devices") Cc: stable@kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241026-fix-sm8x50-mdp-icc-v2-1-fd8ddf755acc@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: qcs8300: Add LLCC support for QCS8300Jingyi Wang1-0/+15
Add Last Level Cache Controller node on the QCS8300 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> Link: https://lore.kernel.org/r/20241031-qcs8300_llcc-v3-3-bb56952cb83b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: qcs8300: Add PMU support for QCS8300Jingyi Wang1-0/+10
Add Performance Monitoring Unit(PMU) nodes on the QCS8300 platform. Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241101-qcs8300_pmu-v1-1-3f3d744a3482@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm8650: add interconnect and opp-peak-kBps for GPUNeil Armstrong1-0/+15
Each GPU OPP requires a specific peak DDR bandwidth, let's add those to each OPP and also the related interconnect path. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241217-topic-sm8x50-gpu-bw-vote-v6-7-1adaf97e7310@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm8550: add interconnect and opp-peak-kBps for GPUNeil Armstrong1-0/+13
Each GPU OPP requires a specific peak DDR bandwidth, let's add those to each OPP and also the related interconnect path. Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241217-topic-sm8x50-gpu-bw-vote-v6-6-1adaf97e7310@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: qcs615-ride: Enable secondary USB controller on QCS615 RideKrishna Kurapati1-0/+36
Enable secondary USB controller on QCS615 Ride platform. The secondary USB controller is made "host", as it is a Type-A port. Secondary USB controller of QCS615 Ride has Type-A port exposed for connecting peripheral. The VBUS to the peripheral is provided by TPS2549IRTERQ1 regulator connected to the port. The regulator has an enable pin controlled by PM8150. Model it as fixed regulator and keep it Always-On at boot, since the regulator is GPIO controlled regulator. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Co-developed-by: Song Xue <quic_songxue@quicinc.com> Signed-off-by: Song Xue <quic_songxue@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241218-add_usb_host_mode_for_qcs615-v3-2-d9d29fe39a4b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: qcs615: Add support for secondary USB node on QCS615Krishna Kurapati1-0/+78
Add support for secondary USB controller and its high-speed phy on QCS615. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Co-developed-by: Song Xue <quic_songxue@quicinc.com> Signed-off-by: Song Xue <quic_songxue@quicinc.com> Link: https://lore.kernel.org/r/20241218-add_usb_host_mode_for_qcs615-v3-1-d9d29fe39a4b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sm7225-fairphone-fp4: Drop extra qcom,msm-id valueLuca Weiss1-1/+1
The ID 434 is for SM6350 while 459 is for SM7225. Fairphone 4 is only SM7225, so drop the unused 434 entry. Fixes: 4cbea668767d ("arm64: dts: qcom: sm7225: Add device tree for Fairphone 4") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241220-fp4-msm-id-v1-1-2b75af02032a@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: sc8280xp: Add Huawei Matebook E Go (sc8280xp)Pengyu Luo2-0/+1319
Add an initial devicetree for the Huawei Matebook E Go, which is based on sc8280xp. There are 3 variants, Huawei released first 2 at the same time. Huawei Matebook E Go LTE(sc8180x), codename should be gaokun2. Huawei Matebook E Go(sc8280xp@3.0GHz), codename is gaokun3. Huawei Matebook E Go 2023(sc8280xp@2.69GHz). We add support for the latter two variants. This work started by Tianyu Gao and Xuecong Chen, they made the devicetree based on existing work(i.e. the Lenovo X13s and the Qualcomm CRD), it can boot with framebuffer. Original work: https://github.com/matalama80td3l/matebook-e-go-boot-works/blob/main/dts/sc8280xp-huawei-matebook-e-go.dts Later, I got my device, I continue their work. Supported features: - adsp - bluetooth (connect issue) - charge (with a lower power) - framebuffer - gpu - keyboard (via internal USB) - pcie devices (wifi and nvme, no modem) - speakers and microphones - tablet mode switch - touchscreen - usb - volume key and power key Some key features not supported yet: - battery and charger information report (EC driver required) - built-in display (cannot enable backlight yet) - charging thresholds control (EC driver required) - camera - LID switch detection (EC driver required) - USB Type-C altmode (EC driver required) - USB Type-C PD (EC driver required) I have finished the EC driver, once this series are upstreamed, I will submit a series of patches to enable EC support. Co-developed-by: Tianyu Gao <gty0622@gmail.com> Signed-off-by: Tianyu Gao <gty0622@gmail.com> Co-developed-by: Xuecong Chen <chenxuecong2009@outlook.com> Signed-off-by: Xuecong Chen <chenxuecong2009@outlook.com> Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Link: https://lore.kernel.org/r/20241220160530.444864-4-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: Add Xiaomi Redmi 5ABarnabás Czémán2-0/+334
Add initial support for Xiaomi Redmi 5A (riva). Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20241221-msm8917-v11-4-901a74db4805@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: Add initial support for MSM8917Otto Pflüger1-0/+1954
Add initial support for MSM8917 SoC. Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de> [reword commit, rebase, fix schema errors] Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Stephan Gerhold <stephan.gerhold@linaro.org> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20241221-msm8917-v11-2-901a74db4805@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: Add PM8937 PMICDang Huynh1-0/+150
The PM8937 features integrated peripherals like ADC, GPIO controller, MPPs, PON keys and others. Add the device tree so that any boards with this PMIC can use it. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Dang Huynh <danct12@riseup.net> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20241221-msm8917-v11-1-901a74db4805@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: x1e80100-qcp: Fix USB QMP PHY suppliesStephan Gerhold1-3/+3
On the X1E80100 QCP, &vreg_l3e_1p2 only powers &usb_mp_qmpphy0/1 (i.e. USBSS_3 and USBSS_4). The QMP PHYs for USB_0, USB_1 and USB_2 are actually powered by &vreg_l2j_1p2. Cc: stable@vger.kernel.org Fixes: 20676f7819d7 ("arm64: dts: qcom: x1e80100-qcp: Fix USB PHYs regulators") Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241210-x1e80100-usb-qmp-supply-fix-v1-8-0adda5d30bbd@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: x1e80100-microsoft-romulus: Fix USB QMP PHY suppliesStephan Gerhold1-2/+2
On the X1E80100 CRD, &vreg_l3e_1p2 only powers &usb_mp_qmpphy0/1 (i.e. USBSS_3 and USBSS_4). The QMP PHYs for USB_0, USB_1 and USB_2 are actually powered by &vreg_l2j_1p2. Since x1e80100-microsoft-romulus mostly just mirrors the power supplies from the x1e80100-crd device tree, assume that the fix also applies here. Cc: stable@vger.kernel.org Fixes: 09d77be56093 ("arm64: dts: qcom: Add support for X1-based Surface Laptop 7 devices") Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241210-x1e80100-usb-qmp-supply-fix-v1-7-0adda5d30bbd@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Fix USB QMP PHY suppliesStephan Gerhold1-3/+3
On the X1E80100 CRD, &vreg_l3e_1p2 only powers &usb_mp_qmpphy0/1 (i.e. USBSS_3 and USBSS_4). The QMP PHYs for USB_0, USB_1 and USB_2 are actually powered by &vreg_l2j_1p2. Since x1e80100-lenovo-yoga-slim7x mostly just mirrors the power supplies from the x1e80100-crd device tree, assume that the fix also applies here. Cc: stable@vger.kernel.org Fixes: 45247fe17db2 ("arm64: dts: qcom: x1e80100: add Lenovo Thinkpad Yoga slim 7x devicetree") Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241210-x1e80100-usb-qmp-supply-fix-v1-6-0adda5d30bbd@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-27arm64: dts: qcom: x1e80100-dell-xps13-9345: Fix USB QMP PHY suppliesStephan Gerhold1-2/+2
On the X1E80100 CRD, &vreg_l3e_1p2 only powers &usb_mp_qmpphy0/1 (i.e. USBSS_3 and USBSS_4). The QMP PHYs for USB_0, USB_1 and USB_2 are actually powered by &vreg_l2j_1p2. Since x1e80100-dell-xps13-9345 mostly just mirrors the power supplies from the x1e80100-crd device tree, assume that the fix also applies here. Cc: stable@vger.kernel.org Fixes: f5b788d0e8cd ("arm64: dts: qcom: Add support for X1-based Dell XPS 13 9345") Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Tested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241210-x1e80100-usb-qmp-supply-fix-v1-5-0adda5d30bbd@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-22 07:43:50 +0300