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2021-09-02Merge tag 'dt-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-7/+95
Pull ARM SoC DT updates from Arnd Bergmann: "As usual, the bulk of work in the SoC tree goes into DT files, this time with a roughly even split between 32-bit and 64-bit SoCs rather than the usual mostly 64-bit changes. New SoCs: - Microchip SAMA7 SoC family based on Cortex-A7, a new 32-bit platform based on the older SAMA5 series. - Qualcomm Snapdragon SDM636 and SM8150, variations of the existing phone SoCs. - Renesas R-Car H3e-2G and M3e-2G SoCs, variations of older Renesas SoCs. New boards: - Marvell CN913x reference boards - ASpeed AST2600 BMC implementations for Facebook Cloudripper, Elbert and Fuji server boards. - Snapdragon 665 based Sony Xperia 10II - Snapdragon MSM8916 based Xiaomi Redmi 2 - Snapdragon MSM8226 based Samsung Galaxy S3 Neo - NXP i.MX based 32-bit boards: - DHCOM based PicoITX - DHSOM based DRC0ỉ - SolidRun SolidSense - SKOV i.MX6 boards. - NXP i.MX based 64-bit boards: - Nitrogen8 SoM and MNT Reform2 - LS1088A based Traverse Ten64 - i.MX8M based GW7902. - NVIDIA Jetson TX2 NX Developer Kit - 4KOpen STiH418-b2264 development board - ux500 based Samsung phones: Gavini, Codina and Kyle - TI AM335x based Sancloud BBE Lite - ixp4xx dts files to replace all old board files Other changes: - Treewide fixes for dtc warnings - Rockchips i/o domain support - TI OMAP/AM3 CPSW switch driver support - Improved device support for allwinner, aspeed, qualcomm, NXP, nvidia, Renesas, Samsung, Amlogic, Mediatek, ixp4xx, stm32, sti, OMAP and actions" * tag 'dt-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (412 commits) arm/arm64: dts: Fix remaining dtc 'unit_address_format' warnings ARM: dts: rockchip: Add SFC to RV1108 arm64: dts: marvell: armada-37xx: Extend PCIe MEM space ARM: dts: aspeed: p10bmc: Add power control pins ARM: dts: aspeed: cloudripper: Add comments for "mdio1" ARM: dts: aspeed: minipack: Update flash partition table dt-bindings: arm: fsl: Add Traverse Ten64 (LS1088A) board dt-bindings: vendor-prefixes: add Traverse Technologies arm64: dts: add device tree for Traverse Ten64 (LS1088A) arm64: dts: ls1088a: add missing PMU node arm64: dts: ls1088a: add internal PCS for DPMAC1 node ARM: dts: imx6qp-prtwd3: configure ENET_REF clock to 125MHz ARM: dts: vf610-zii-dev-rev-b: Remove #address-cells and #size-cells property from at93c46d dt node ARM: dts: add SKOV imx6q and imx6dl based boards dt-bindings: arm: fsl: add SKOV imx6q and imx6dl based boards dt-bindings: vendor-prefixes: Add an entry for SKOV A/S arm64: dts: imx8mq-reform2: add sound support arm64: dts: imx8m: drop interrupt-affinity for pmu arm64: dts: imx8qxp: update pmu compatible arm64: dts: imx8mm: update pmu compatible ...
2021-08-17Merge tag 'v5.14-rc3' into arm64-for-5.15Bjorn Andersson1-1/+1
The USB maintainer felt the strong need to push '1f958f3dff42 ("Revert "arm64: dts: qcom: Harmonize DWC USB3 DT nodes name"")' through the usb tree, so merge v5.14-rc3 to resolve the resulting merge conflicts. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-16arm64: dts: sc7180: Add required-opps for i2cRajendra Nayak1-0/+24
qup-i2c devices on sc7180 are clocked with a fixed clock (19.2 MHz) Though qup-i2c does not support DVFS, it still needs to vote for a performance state on 'CX' to satisfy the 19.2 Mhz clock frequency requirement. Use 'required-opps' to pass this information from device tree, and also add the power-domains property to specify the CX power-domain. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-08-05arm64: dts: qcom: sc7180: assign DSI clock source parentsDmitry Baryshkov1-0/+3
Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210709210729.953114-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-05arm64: dts: qcom: sc7180: define ipa_fw_mem nodeAlex Elder1-0/+5
Define the reserved memory space used for IPA firmware for the Qualcomm SC7180 SoC. Signed-off-by: Alex Elder <elder@linaro.org> Link: https://lore.kernel.org/r/20210804210214.1891755-4-elder@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-05arm64: dts: qcom: sc7180: Update lpass cpu node for audio over dpV Sujith Kumar Reddy1-6/+10
Updaate lpass dts node with HDMI reg, interrupt and iommu for supporting audio over dp. Signed-off-by: V Sujith Kumar Reddy <vsujithk@codeaurora.org> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@qti.qualcomm.com> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210721080549.28822-2-srivasam@qti.qualcomm.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-05arm64: dts: qcom: sc7180:: modified qfprom CORR size as per RAW sizeRavi Kumar Bokka1-1/+1
modified QFPROM controller CORRECTED region size as per RAW region size Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/1613582792-5225-1-git-send-email-rbokka@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-07-21Revert "arm64: dts: qcom: Harmonize DWC USB3 DT nodes name"Greg Kroah-Hartman1-1/+1
This reverts commit eb9b7bfd5954f5f6ac4d57313541dd0294660aad as it breaks working userspace implementations (i.e. Android systems) The device node name here is part of configfs, so it is a user-visable api that can not be changed. Reported-by: John Stultz <john.stultz@linaro.org> Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/CALAqxLX_FNvFndEDWtGbFPjSzuAbfqxQE07diBJFZtftwEJX5A@mail.gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-07-19arm64: dts: qcom: sc7180: Add DisplayPort nodeKuogee Hsieh1-0/+76
Add DP device node on sc7180. Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1622758940-13485-1-git-send-email-khsieh@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-18arm64: dts: qcom: sc7180: bus votes for eMMC and SD cardShaik Sajida Bhanu1-10/+10
Update peak bandwidth and average bandwidth vote values for eMMC and SDCard. This patch calculates the new votes as per the comments from https://lore.kernel.org/patchwork/patch/1399453/#1619566. Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Link: https://lore.kernel.org/r/1623835344-29607-1-git-send-email-sbhanu@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-14arm64: dts: qcom: sc7180: Add xo clock for eMMC and Sd cardShaik Sajida Bhanu1-4/+6
The calculations for the DLL register values are based on the clock rate of the reference clock. Provide the reference clock in the definition of the two SDHCI controllers to not rely on the default values. Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Link: https://lore.kernel.org/r/1623309107-27833-1-git-send-email-sbhanu@codeaurora.org [bjorn: Rewrote commit message] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-06arm64: dts: qcom: sc7180: Move sdc pinconf to board specific DT filesSujit Kautkar1-102/+0
Move sdc1/sdc2 pinconf from SoC specific DT file to board specific DT files Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Sujit Kautkar <sujitka@chromium.org> Link: https://lore.kernel.org/r/20210602121313.v3.1.Ia83c80aec3b9535f01441247b6c3fb6f80b0ec7f@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-05-31arm64: dts: qcom: sc7180: Fix sc7180-qmp-usb3-dp-phy reg sizesDouglas Anderson1-2/+2
As per Dmitry Baryshkov [1]: a) The 2nd "reg" should be 0x3c because "Offset 0x38 is USB3_DP_COM_REVISION_ID3 (not used by the current driver though)." b) The 3rd "reg" "is a serdes region and qmp_v3_dp_serdes_tbl contains registers 0x148 and 0x154." I think because the 3rd "reg" is a serdes region we should just use the same size as the 1st "reg"? [1] https://lore.kernel.org/r/ee5695bb-a603-0dd5-7a7f-695e919b1af1@linaro.org Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Rob Clark <robdclark@chromium.org> Fixes: 58fd7ae621e7 ("arm64: dts: qcom: sc7180: Update dts for DP phy inside QMP phy") Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210315103836.1.I9a97120319d43b42353aeac4d348624d60687df7@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-05-31arm64: dts: qcom: Harmonize DWC USB3 DT nodes nameSerge Semin1-1/+1
In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210324204836.29668-8-Sergey.Semin@baikalelectronics.ru Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-05-31arm64: dts: qcom: sc7180: Remove QUP-CORE ICC pathRoja Rani Yarubandi1-4/+0
We had introduced the QUP-CORE ICC path to put proxy votes from QUP wrapper on behalf of earlycon, if other users of QUP-CORE turn off this clock before the real console is probed, unclocked access to HW was seen from earlycon. With ICC sync state support proxy votes are no longer need as ICC will ensure that the default bootloader votes are not removed until all it's consumer are probed. We can safely remove ICC path for QUP-CORE clock from QUP wrapper device. Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Signed-off-by: Akash Asthana <akashast@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/20210324101836.25272-3-rojay@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-04-19arm64: dts: qcom: sc7180: Update iommu property for simultaneous playbackV Sujith Kumar Reddy1-1/+2
Update iommu property in lpass cpu node for supporting simultaneous playback on headset and speaker. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: V Sujith Kumar Reddy <vsujithk@codeaurora.org> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Link: https://lore.kernel.org/r/20210406163330.11996-1-srivasam@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-04-04arm64: dts: qcom: Move rmtfs memory regionSujit Kautkar1-2/+2
Move rmtfs memory region so that it does not overlap with system RAM (kernel data) when KAsan is enabled. This puts rmtfs right after mba_mem which is not supposed to increase beyond 0x94600000 Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Sujit Kautkar <sujitka@chromium.org> Link: https://lore.kernel.org/r/20210330014610.1451198-1-sujitka@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-12arm64: dts: qcom: sc7180: Use pdc interrupts for USB instead of GIC interruptsSandeep Maheswaram1-4/+4
Using pdc interrupts for USB instead of GIC interrupts to support wake up in case xo shutdown. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Link: https://lore.kernel.org/r/1594235417-23066-4-git-send-email-sanm@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-12arm64: dts: qcom: Move sc7180 MI2S config to board files and make pulldownDouglas Anderson1-18/+0
In general pinconf belongs in board files, not SoC files. Move it to the only current user (trogdor). Also adjust the drive strengths and pulls. Cc: V Sujith Kumar Reddy <vsujithk@codeaurora.org> Cc: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.2.Id27e7e6f90c29bf623fa4880e18a14ba1dffd2d2@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-12arm64: dts: qcom: sc7180: Update dts for DP phy inside QMP phyStephen Boyd1-7/+16
Drop the old node and add the new one in its place. Cc: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Rob Clark <robdclark@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> [dianders: Adjusted due to DP not itself not in upstream dts yet] Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.1.Iad06142ceb8426ce5492737bf3d9162ed0dd2b55@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-12arm64: dts: qcom: sc7180: Rename the qmp node to power-controllerSai Prakash Ranjan1-1/+1
Use the generic DT node name "power-controller" for AOSS message ram instead of the protocol name QMP(Qualcomm Messaging Protocol) since it is used for power management requests. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/e96d665d1e98b46a189a57e39575ae0debf37172.1614669585.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-02-21Merge tag 'arm-dt-v5.12' of ↵Linus Torvalds1-16/+33
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC devicetree updates from Arnd Bergmann: "After the last release contained a surprising amount of new 32-bit machines, this time two thirds of the code changes are for 64-bit. The usual updates to existing files include: - Device tree compiler warning fixes for Berlin, Renesas, SoCFPGA, nomadik, stm32, Allwinner, TI Keystone - Support for additional devices on existing machines on Renesas, SoCFPGA, at91, hisilicon, OMAP, Tegra, TI K3, Allwinner, Broadcom, ux500, Mediatek, Marvell Armada, Marvell MMP, ZynqMP, AMLogic, Qualcomm, i.MX, Layerscape, Actions, ASpeed, Toshiba - Cleanups and minor fixes for Renesas, at91, mstar, ux500, Samsung, stm32, Tegra, Broadcom, Mediatek, Marvell MMP, AMLogic, Qualcomm, i.MX, Rockchip, ASpeed, Zynq Only three new SoCs this time, but a number of boards across: Renesas: - Two Beacon EmbeddedWorks boards (RZ/G2H and RZ/G2N based) Intel SoCFPGA: - eASIC N5X board (N5X) ST-Ericsson Ux500: - Samsung GT-I9070 (Janice) phone (u8500) TI OMAP: - MYIR Tech Limited development board (AM335X) Allwinner/sunxi: - SL631 Action Camera (V3) - PineTab Early Adopter tablet (A64) Broadcom: - BCM4906 networking chip - Netgear R8000P router (BCM4906) AMLogic: - Hardkernel ODROID-HC4 development board (SM1) - Beelink GS-King-X TV Box (S922X) Qualcomm: - Snapdragon 888 / SM8350 high-end phone SoC - Qualcomm SDX55 5G modem as standalone SoC - Snapdragon MTP reference board (SM8350) - Snapdragon MTP reference board (SDX55) - Sony Kitakami phones: Xperia Z3+/Z4/Z5 (APQ8094) - Alcatel Idol 3 phone (MSM8916) - ASUS Zenfone 2 Laser phone (MSM8916) - BQ Aquaris X5 aka Longcheer L8910 phone (MSM8916) - OnePlus6 phone (SDM845) - OnePlus6T phone (SDM845) - Alfa Network AP120C-AC access point (IPQ4018) NXP i.MX6 (32-bit): - Plymovent BAS base system controller for filter systems (imx6dl) - Protonic MVT industrial touchscreen terminals (imx6dl) - Protonic PRTI6G reference board (imx6ul) - Kverneland UT1, UT1Q, UT1P, TGO agricultural terminals (imx6q/dl/qp) NXP i.MX8 (64-bit) - Beacon i.MX8M Nano development kit (imx8mn) - Boundary Devices i.MX8MM Nitrogen SBC (imx8mm) - Gateworks Venice i.MX 8M Mini Development Kits (imx8mm) - phyBOARD-Pollux-i.MX8MP (imx8mp) - Purism Librem5 Evergreen phone (imx8mp) - Kontron SMARC-sAL28 system-on-module(imx8mp) Rockchip: - NanoPi M4B Single-board computer (RK3399) - Radxa Rock Pi E router SBC (RK3328) ASpeed: - Ampere Mt. Jade, a BMC for an x86 server (AST2500) - IBM Everest, a BMC for a Power10 server (AST2600) - Supermicro x11spi, a BMC for an ARM server (AST2500) Zynq: - Ebang EBAZ4205, FPGA board (Zynq-7000) - ZynqMP zcu104 revC reference platform (ZynqMP)" * tag 'arm-dt-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (584 commits) ARM: dts: aspeed: align GPIO hog names with dtschema ARM: dts: aspeed: fix PCA95xx GPIO expander properties on Portwell dt-bindings: spi: zynq: Convert Zynq QSPI binding to yaml arm: dts: visconti: Add DT support for Toshiba Visconti5 GPIO driver ARM: dts: aspeed: ast2600evb: Add enable ehci and uhci ARM: dts: aspeed: mowgli: Add i2c rtc device ARM: dts: aspeed: amd-ethanolx: Enable secondary LPC snooping address dt-bindings: arm: xilinx: Add missing Zturn boards ARM: dts: ebaz4205: add pinctrl entries for switches ARM: dts: add Ebang EBAZ4205 device tree dt-bindings: arm: add Ebang EBAZ4205 board dt-bindings: add ebang vendor prefix ARM: dts: aspeed: Add Everest BMC machine ARM: dts: aspeed: inspur-fp5280g2: Add ipsps1 driver ARM: dts: aspeed: inspur-fp5280g2: Add GPIO line names ARM: dts: aspeed: Add Supermicro x11spi BMC machine ARM: dts: aspeed: g220a: Fix some gpio ARM: dts: aspeed: g220a: Enable ipmb ARM: dts: aspeed: rainier: Add eMMC clock phase compensation ARM: dts: aspeed: Add LCLK to lpc-snoop ...
2021-02-03arm64: dts: qcom: sc7180: Add support for gpu fuseAkhil P Oommen1-0/+22
Add support for gpu fuse to help identify the supported opps. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/1610129731-4875-2-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-26arm64: dts: qcom: sc7180: Add watchdog bark interruptSai Prakash Ranjan1-0/+1
Specify bark interrupt for APSS watchdog to support pre-timeout notification on SC7180 SoC. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/535b368f6c22bab7078842d803a73e695f28a751.1611466260.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-22arm64: dts: qcom: sc7180: kill IPA modem-remoteproc propertyAlex Elder1-2/+0
The "modem-remoteproc" property is no longer required for the IPA driver, so get rid of it. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-01-15arm64: dts: qcom: sc7180: Add labels for cpuN-thermal nodesMatthias Kaehlcke1-10/+10
Add labels to the cpuN-thermal nodes to allow board files to use a phandle instead replicating the node hierarchy when adjusting certain properties. Due to the 'sustainable-power' property CPU thermal zones are more likely to need property updates than other SC7180 zones, hence only labels for CPU zones are added for now. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/20210108141648.1.Ia8019b8b303ca31a06752ed6ceb5c3ac50bd1d48@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-28arm64: dts: qcom: sc7180: Drop pinconf on dp_hot_plug_detStephen Boyd1-6/+0
We shouldn't put any pinconf here in case someone decides to invert this HPD signal or remove an external pull-down. It's better to leave that to the board pinconf nodes, so drop it here. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reported-by: Douglas Anderson <dianders@chromium.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Fixes: 681a607ad21a ("arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20201215020004.731239-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driverAjit Pandey1-0/+69
Add the I2S controller node to sc7180 dtsi. Add pinmux for primary and secondary I2S. Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Ajit Pandey <ajitp@codeaurora.org> Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Signed-off-by: V Sujith Kumar Reddy <vsujithk@codeaurora.org> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Link: https://lore.kernel.org/r/1600450426-14063-1-git-send-email-srivasam@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-26arm64: dts: qcom: sc7180: use GIC_SPI for IPA interruptsAlex Elder1-2/+2
Use GIC_SPI rather than 0 in the specifiers for the two ARM GIC interrupts used by IPA. Signed-off-by: Alex Elder <elder@linaro.org> Link: https://lore.kernel.org/r/20201126015457.6557-3-elder@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-26arm64: dts: qcom: sc7180: limit IPA iommu streamsAlex Elder1-1/+2
Recently we learned that Android and Windows firmware don't seem to like using 3 as an iommu mask value for IPA. A simple fix was to specify exactly the streams needed explicitly, rather than implying a range with the mask. Make the same change for the SC7180 platform. See also: https://lore.kernel.org/linux-arm-msm/20201123052305.157686-1-bjorn.andersson@linaro.org/ Fixes: d82fade846aa8 ("arm64: dts: qcom: sc7180: add IPA information") Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Alex Elder <elder@linaro.org> Link: https://lore.kernel.org/r/20201126015457.6557-2-elder@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-25arm64: dts: qcom: sc7180: Add DDR/L3 votes for the pro variantSibi Sankar1-0/+5
Add DDR/L3 bandwidth votes for the pro variant of SC7180 SoC, as it support frequencies upto 2.5 GHz. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/1606198876-3515-2-git-send-email-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-23arm64: dts: qcom: sc7180: Set 'polling-delay-passive' for thermal zones back ↵Matthias Kaehlcke1-25/+25
to 250 ms Commit 22337b91022d ("arm64: dts: qcom: sc7180: Changed polling mode in Thermal-zones node") sets both 'polling-delay' and 'polling-delay-passive' to zero with the rationale that TSENS interrupts are enabled. A TSENS interrupt fires when the temperature of a thermal zone reaches a trip point, which makes regular polling below the passive trip point temperature unnecessary. However the situation is different when passive cooling is active, regular polling is still needed to trigger a periodic evaluation of the thermal zone by the thermal governor. Change 'polling-delay-passive' back to the original value of 250 ms. Commit 2315ae70af95 ("arm64: dts: qcom: sc7180: Add gpu cooling support") recently changed the value for the GPU thermal zones from zero to 100 ms, also set it to 250 ms for uniformity. If some zones really need different values these can be changed in dedicated patches. Reviewed-by: Douglas Anderson <dianders@chromium.org> Fixes: 22337b91022d ("arm64: dts: qcom: sc7180: Changed polling mode in Thermal-zones node") Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/20201111120334.1.Ifc04ea235c3c370e3b21ec3b4d5dead83cc403b4@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-11arm64: dts: qcom: sc7180: Assign numbers to eMMC and SDDouglas Anderson1-0/+2
After many years of struggle, commit fa2d0aa96941 ("mmc: core: Allow setting slot index via device tree alias") finally allows the use of aliases to number SD/MMC slots. Let's do that for sc7180 SoCs so that if eMMC and SD are both used they have consistent numbers across boots and kernel changes. Picking numbers can be tricky. Do we call these "1" and "2" to match the name in documentation or "0" and "1" with the assertion that we should always start at 0 and count up? While the "start counting at 0" makes sense if there are not already well-defined numbers for all sd/mmc controllers, in the case of sc7180 there _are_ well defined numbers. IMO it is less confusing to use those and match the docs. Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20201111073652.1.Ia5bccd9eab7d74ea1ea9a7780e3cdbf662f5a464@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-11arm64: dts: qcom: sc7180: Add gpu cooling supportAkhil P Oommen1-7/+23
Add cooling-cells property and the cooling maps for the gpu tzones to support GPU cooling. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1604054832-3114-2-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-11arm64: dts: sc7180: Add camera clock controller nodeTaniya Das1-0/+12
Add the camera clock controller node supported on SC7180. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1604687907-25712-1-git-send-email-tdas@codeaurora.org [bjorn: Dropped camcc include] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-10arm: dts: qcom: sc7180: Set the compatible string for the GPU SMMURob Clark1-1/+1
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable split pagetables and per-instance pagetables for drm/msm. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200905200454.240929-21-robdclark@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-02arm64: dts: qcom: sc7180: Add soc-specific qfprom compat stringEvan Green1-1/+1
Add the soc-specific compatible string so that it can be matched more specifically now that the driver cares which SoC it's on. Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20201028172737.v3.2.Ia3b68ac843df93c692627a3a92b947b3a5785863@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-10-27arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CSDouglas Anderson1-0/+104
When the chip select line is controlled by the QUP, changing CS is a time consuming operation. We have to send a command over to the geni and wait for it to Ack us every time we want to change (both making it high and low). To send this command we have to make a choice in software when we want to control the chip select, we have to either: A) Wait for the Ack via interrupt which slows down all SPI transfers (and incurrs extra processing associated with interrupts). B) Sit in a loop and poll, waiting for the Ack. Neither A) nor B) is a great option. We can avoid all of this by realizing that, at least on some boards, there is no advantage of considering this line to be a geni line. While it's true that geni _can_ control the line, it's also true that the line can be a GPIO and there is no downside of viewing it that way. Setting a GPIO is a simple MMIO operation. This patch provides definitions so a board can easily select the GPIO mode. NOTE: apparently, it's possible to run the geni in "GSI" mode. In GSI the SPI port is allowed to be controlled by more than one user (like firmware and Linux) and also the port can operate sequences of operations in one go. In GSI mode it _would_ be invalid to look at the chip select as a GPIO because that would prevent other users from using it. In theory GSI mode would also avoid some overhead by allowing us to sequence the chip select better. However, I'll argue GSI is not relevant for all boards (and certainly not any boards supported by mainline today). Why? - Apparently to run a SPI chip in GSI mode you need to initialize it (in the bootloader) with a different firmware and then it will always run in GSI mode. Since there is no support for GSI mode in the current Linux driver, it must be that existing boards don't have firmware that's doing that. Note that the kernel device tree describes hardware but also firmware, so it is legitimate to make the assumption that we don't have GSI firmware in a given dts file. - Some boards with sc7180 have SPI connected to the Chrome OS EC or security chip (Cr50). The protocols for talking to cros_ec and cr50 are extremely complex. Both drivers in Linux fully lock the bus across several distinct SPI transfers. While I am not an expert on GSI mode it feels highly unlikely to me that we'd ever be able to enable GSI mode for these devices. From a testing perspective, running "flashrom -p ec -r /tmp/foo.bin" in a loop after this patch shows almost no reduction in time, but the number of interrupts per command goes from 32357 down to 30611 (about a 5% reduction). Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Akash Asthana <akashast@codeaurora.org> Link: https://lore.kernel.org/r/20200921142655.v3.1.I997a428f58ef9d48b37a27a028360f34e66c00ec@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-10-26arm64: dts: qcom: sc7180: Fix one forgotten interconnect referenceDouglas Anderson1-1/+1
In commit e23b1220a246 ("arm64: dts: qcom: sc7180: Increase the number of interconnect cells") we missed increasing the cells on one interconnect. That's no bueno. Fix it. NOTE: it appears that things aren't totally broken without this fix, but clearly something isn't going to be working right. If nothing else, without this fix I see this in the logs: OF: /soc@0/mdss@ae00000: could not get #interconnect-cells for /soc@0/interrupt-controller@17a00000 Fixes: e23b1220a246 ("arm64: dts: qcom: sc7180: Increase the number of interconnect cells") Reviewed-by: Georgi Djakov <georgi.djakov@linaro.org> Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20201001141838.1.I08054d1d976eed64ffa1b0e21d568e0dc6040b54@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-16arm64: dts: qcom: sc7180: Increase the number of interconnect cellsSibi Sankar1-109/+109
Increase the number of interconnect-cells, as now we can include the tag information. The consumers can specify the path tag as an additional argument to the endpoints. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Tested-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Link: https://lore.kernel.org/r/20200903133134.17201-8-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-14arm64: dts: qcom: sc7180: Drop flags on mdss irqsStephen Boyd1-2/+2
The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two where the second cell is the irq flags. Drop the second cell to match the binding. Cc: Kalyan Thota <kalyan_t@codeaurora.org> Cc: Harigovindan P <harigovi@codeaurora.org Fixes: a3db7ad1af49 ("arm64: dts: sc7180: add display dt nodes") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20200811192503.1811462-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-11arm64: dts: sc7180: add bus clock to mdp node for sc7180 targetKrishna Manikandan1-4/+4
Move the bus clock to mdp device node,in order to facilitate bus band width scaling on sc7180 target. The parent device MDSS will not vote for bus bw, instead the vote will be triggered by mdp device node. Since a minimum vote is required to turn on bus clock, move the clock node to mdp device from where the votes are requested. This patch has dependency on the below series https://patchwork.kernel.org/patch/11468783/ Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> Link: https://lore.kernel.org/r/1594899334-19772-2-git-send-email-kalyan_t@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-11arm64: dts: qcom: sc7180: Add bandwidth votes for eMMC and SDcardPradeep P V K1-0/+15
Add the bandwidth domain supporting performance state and the corresponding OPP tables for the sdhc device on sc7180. Signed-off-by: Pradeep P V K <ppvk@codeaurora.org> Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Link: https://lore.kernel.org/r/1597646464-1863-1-git-send-email-sbhanu@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-11arm64: dts: qcom: sc7180: Add 'sustainable_power' for CPU thermal zonesMatthias Kaehlcke1-0/+10
The 'sustainable_power' attribute provides an estimate of the sustained power that can be dissipated at the desired control temperature. One could argue that this value is not necessarily the same for all devices with the same SoC, which may have different form factors or thermal designs. However there are reasons to specify a (default) value at SoC level for SC7180: most importantly, if no value is specified at all the power_allocator thermal governor (aka 'IPA') estimates a value, using the minimum power of all cooling devices of the zone, which can result in overly aggressive thermal throttling. For most devices an approximate conservative value should be more useful than the minimum guesstimate of power_allocator. Devices that need a different value can overwrite it in their <device>.dts. Also the thermal zones for SC7180 have a high level of granularity (essentially one for each function block), which makes it more likely that the default value just works for many devices. The values correspond to 1901 MHz for the big cores, and 1804 MHz for the small cores. The values were determined by limiting the CPU frequencies to different max values and launching a bunch of processes that cause high CPU load ('while true; do true; done &' is simple and does a good job). A frequency is deemed sustainable if the CPU temperatures don't rise (consistently) above the second trip point ('control temperature', 95 degC in this case). Once the highest sustainable frequency is found, the sustainable power can be calculated by multiplying the energy consumption per core at this frequency (which can be found in /sys/kernel/debug/energy_model/) with the number of cores that are specified as cooling devices. The sustainable frequencies were determined at room temperature on a device without heat sink or other passive cooling elements. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/20200813113030.1.I89c33c4119eaffb986b1e8c1bc6f0e30267089cd@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-11arm64: dts: qcom: sc7180: Add OPP tables and power-domains for venusRajendra Nayak1-2/+33
Add the OPP tables in order to be able to vote on the performance state of a power-domain Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1598970026-7199-6-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-11arm64: dts: qcom: sc7180: add interconnect bindings for displayKrishna Manikandan1-0/+3
This change adds the interconnect bindings to the MDSS node. This will establish Display to DDR path for bus bandwidth voting. Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> Link: https://lore.kernel.org/r/1594899334-19772-1-git-send-email-kalyan_t@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10arm64: dts: qcom: sc7180: Add LPASS clock controller nodesTaniya Das1-0/+24
Update the clock controller nodes for Low power audio subsystem functionality. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1596305615-5894-2-git-send-email-tdas@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-08-30arm64: dts: qcom: sc7180: Fix the LLCC base register sizeSai Prakash Ranjan1-1/+1
There is one LLCC logical bank(LLCC0) on SC7180 SoC and the size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct the size and fix copy paste mistake carried over from SDM845. Reviewed-by: Douglas Anderson <dianders@chromium.org> Fixes: 7cee5c742899 ("arm64: dts: qcom: sc7180: Fix node order") Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node") Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/20200818145514.16262-1-saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-08-30arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt nodeTanmay Shah1-0/+13
This node defines alternate DP HPD functionality of GPIO. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Tanmay Shah <tanmay@codeaurora.org> Link: https://lore.kernel.org/r/20200818033657.16074-1-tanmay@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-28arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU oppSharat Masetty1-0/+7
Add opp-peak-kBps bindings to the GPU opp table, listing the peak GPU -> DDR bandwidth requirement for each opp level. This will be used to scale the DDR bandwidth along with the GPU frequency dynamically. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/1594992579-20662-7-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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