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2022-11-21arm64: tegra: Use vbus-gpios propertyThierry Reding1-2/+2
Instead of using the deprecated vbus-gpio property, switch to using the more standard vbus-gpios property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Restructure Tegra210 PMC pinmux nodesThierry Reding1-21/+19
The PMC pinmux configuration nodes need to be part of a top-level pinmux node. Add that new "pinmux" node and move the configuration nodes into it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Update cache propertiesPierre Gondois3-0/+49
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove 'enable-active-low'Fabio Estevam1-1/+0
The 'enable-active-low' property is not a valid one. Only 'enable-active-high' is valid, and when this property is absent the gpio regulator will act as active low by default. Remove the invalid 'enable-active-low' property. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add dma-channel-mask in GPCDMA nodeAkhil R3-3/+9
Add dma-channel-mask property in Tegra GPCDMA device tree node. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. This is wrong and does not align with the hardware. Correct this and update the interrupts property to list all 32 interrupts. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controllerVidya Sagar1-1/+1
Fix the starting address of the non-prefetchable aperture of PCIe C3 controller. Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add missing compatible string to Ethernet USB deviceThierry Reding1-0/+1
According to the DT schema in usb-device.yaml, each USB device node needs a compatible string, so add one for the built-in USB Ethernet device on Jetson TX1. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Separate AON pinmux from main pinmux on Tegra194Thierry Reding1-3/+10
The registers for the AON pinmux reside in a partition different from the registers for the main pinmux. Instead of treating them as one and the same device, split them up so that they are each their own devices. Also add gpio-ranges properties to the corresponding GPIO controllers such that the pinmux and GPIO controllers can be paired up properly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add ECAM aperture info for all the PCIe controllersVidya Sagar1-22/+33
Add the ECAM aperture information for all the PCIe controllers of Tegra234. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove clock-names from PWM nodesThierry Reding4-25/+0
The Tegra PWFM controllers use a single clock, so there's no need for a clock-names property. Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Enable GTE nodesDipen Patel1-0/+20
Add and enable AON and LIC GTE nodes by default. Signed-off-by: Dipen Patel <dipenp@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Update console for Jetson Xavier and OrinJon Hunter3-3/+3
The Tegra Combined UART (TCU) is the default serial interface for Jetson Xavier and Orin platforms and so update the bootargs for these platforms to use the TCU. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Enable PWM users on Jetson AGX OrinSandipan Patra1-0/+14
Enable additional PWM controllers in device tree so that the PWM pins on the Jetson AGX Orin Developer Kit 40-pin header can be used. Signed-off-by: Sandipan Patra <spatra@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add missing whitespaceThierry Reding1-1/+1
The unit-address of a node should be separated from the opening brace by a space. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Sort nodes by unit-addressThierry Reding1-192/+192
The P2U nodes that were recently added were not added in the correct order. Sort them in the right place by unit-address. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add Tegra234 SDMMC1 device tree nodePrathamesh Shete2-0/+63
Add device tree node for Tegra234 SDMMC1 instance. Add and enable SD card instance in device tree. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add SBSA UART for Tegra234Jon Hunter2-0/+12
Populate the SBSA UART for Tegra234 and enable this UART for Jetson AGX Orin. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add PWM fan for Jetson AGX OrinJon Hunter1-0/+14
Add the PWM fan node for the Tegra234 Jetson AGX Orin platform. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Populate Tegra234 PWMsJon Hunter1-2/+78
Populate all the PWM devices for Tegra234. Finally, update the compatible string for the existing 'pwm1' node to just be 'tegra194-pwm' and remove the fallback to 'tegra186-pwm', which aligns with the binding documentation. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove unused property for I2CJon Hunter1-1/+0
Commit 156af9de0932 ("arm64: tegra: Add Tegra234 I2C devicetree nodes") populated the I2C device nodes for Tegra234. One of these nodes contains the property 'nvidia,hw-instance-id' which is neither documented or used. Remove this unused property. Fixes: 156af9de0932 ("arm64: tegra: Add Tegra234 I2C devicetree nodes") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Fix Prefetchable aperture ranges of Tegra234 PCIe controllersVidya Sagar1-3/+3
commit edf408b946d3 ("PCI: dwc: Validate iATU outbound mappings against hardware constraints") exposes an issue with the existing partitioning of the aperture space where the Prefetchable apertures of controllers C5, C7 and C9 in Tegra234 cross the 32GB boundary hardware constraint. This patch makes sure that the Prefetchable region doesn't spill over the 32GB boundary. Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add NVDEC on Tegra234Mikko Perttunen1-0/+36
Add a device tree node for NVDEC on Tegra234. Booting the firmware requires some information regarding offsets within the firmware binary. These are passed through the device tree, but since the values vary depending on the firmware version, and the firmware itself is not available to the OS, the flasher is expected to provide a device tree overlay with values corresponding to the firmware it is flashing. The overlay then replaces the placeholder values here. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Fix ranges for host1x nodesMikko Perttunen2-2/+2
The currently specified 'ranges' properties don't actually include all devices under the host1x bus on Tegra194 and Tegra234. Expand them appropriately. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add GPCDMA support for Tegra I2CAkhil R3-0/+96
Add dma properties to support GPCDMA for I2C in Tegra 186 and later chips Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add iommus for HDA on Tegra234Mohan Kumar1-0/+1
Add the iommus property to the HDA node on Tegra234. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Enable HDA node for Jetson AGX OrinMohan Kumar1-0/+1
Enable HDA node for the Jetson AGX Orin platform. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add context isolation domains on Tegra234Mikko Perttunen1-0/+18
Add Host1x context isolation domains on Tegra234. On Tegra234 we have two IOMMUs that are connected to Host1x-channel programmed engines, so we have to include domains for each of them. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Fixup iommu-map property formattingThierry Reding2-18/+16
Make sure that each phandle-array is enclosed in a set of angular brackets and properly indent each entry. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: dts: tegra: smaug: Add Wi-Fi nodeDiogo Ivo1-0/+19
The Google Pixel C contains a BRCM4354 Wi-Fi + BT module. Add a DT node for its Wi-Fi functionality. Tested on Pixel C. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: dts: tegra: smaug: Add Bluetooth nodeDiogo Ivo1-0/+17
The Google Pixel C contains a BRCM4354 Wi-Fi + BT module. Add a DT node for its BT functionality. Tested on Pixel C. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Enable MGBE on Jetson AGX Orin Developer KitThierry Reding1-0/+21
A Multi-Gigabit Ethernet (MGBE) instance drives the primary Ethernet port on the Jetson AGX Orin Developer Kit. Enable it. Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add MGBE nodes on Tegra234Thierry Reding1-0/+136
Add device tree nodes for the four instances of the Multi-Gigabit Ethernet (MGBE) IP found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Fix up compatible for Tegra234 GPCDMAThierry Reding1-1/+0
There is no need to list the Tegra194-specific compatible for Tegra234 because the backwards-compatibility goes back all the way to Tegra186. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Enable PCIe slots in P3737-0000 boardVidya Sagar1-0/+51
Enable PCIe controller nodes to enable respective PCIe slots on P3737-0000 board. Following is the ownership of slots by different PCIe controllers. Controller-1 : On-board Broadcom WiFi controller Controller-4 : M.2 Key-M slot Controller-5 : CEM form-factor x8 slot Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DTVidya Sagar1-0/+927
Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree. The Tegra234 SoC contains 10 PCIe controllers and 24 P2U instances grouped into three different PHY bricks namely High-Speed IO (HSIO-8 P2Us) NVIDIA High Speed (NVHS-8 P2Us) and Gigabit Ethernet (GBE-8 P2Us) respectively. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add regulators required for PCIeVidya Sagar1-0/+36
Add regulator supplies required for PCIe functionality. The supplies include 1.8V, 3.3V and 12V. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Fix SDMMC1 CD on P2888Tamás Szűcs1-1/+1
Hook SDMMC1 CD up with CVM GPIO02 (SOC_GPIO11) used for card detection on J4 (uSD socket) on the carrier. Fixes: ef633bfc21e9 ("arm64: tegra: Enable card detect for SD card on P2888") Signed-off-by: Tamás Szűcs <tszucs@protonmail.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Update compatible for Tegra234 GPCDMAAkhil R1-2/+3
Use the compatible specific to Tegra234 for GPCDMA to support additional features. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add Host1x and VIC on Tegra234Mikko Perttunen1-0/+46
Add device tree nodes for Host1x and VIC on Tegra234. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add Host1x context stream IDs on Tegra186+Mikko Perttunen2-0/+22
Add Host1x context stream IDs on systems that support Host1x context isolation. Host1x and attached engines can use these stream IDs to allow isolation between memory used by different processes. The specified stream IDs must match those configured by the hypervisor, if one is present. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Enable native timers on Tegra234Kartik1-0/+22
The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add and enable the device tree node on Tegra234. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Enable native timers on Tegra194Thierry Reding1-0/+16
The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add and enable the device tree node on Tegra194. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Enable native timers on Tegra186Kartik1-1/+1
Enable the native timers on Tegra186 chips to allow using the watchdog functionality to recover from system hangs. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add node for CBB 2.0 on Tegra234Sumit Gupta1-0/+42
Tegra234 uses the Control Backbone (CBB) version 2.0. Add the nodes that enable error handling from the various CBB 2.0 fabrics found on Tegra234. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add node for CBB 1.0 on Tegra194Sumit Gupta1-1/+61
Add device tree nodes to enable error handling on the Control Backbone (CBB). Tegra194 uses CBB version 1.0. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Align gpio-keys node names with dtschemaKrzysztof Kozlowski10-26/+26
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Mark BPMP channels as no-memory-wcMikko Perttunen3-0/+3
The Tegra SYSRAM contains regions access to which is restricted to certain hardware blocks on the system, and speculative accesses to those will cause issues. Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted to resolve this by only mapping the regions specified in the device tree on the assumption that there are no such restricted areas within the 64K-aligned area of memory that contains the memory we wish to map. Turns out this assumption is wrong, as there are such areas above the 4K pages described in the device trees. As such, we need to use the bigger hammer that is no-memory-wc, which causes the memory to be mapped as Device memory to which speculative accesses are disallowed. As such, the previous patch in the series, 'firmware: tegra: bpmp: do only aligned access to IPC memory area', is required with this patch to make the BPMP driver only issue aligned memory accesses as those are also required with Device memory. Fixes: fec29bf04994 ("misc: sram: Only map reserved areas in Tegra SYSRAM") Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Yousaf Kaukab <ykaukab@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add Tegra234 GPCDMA device tree nodeAkhil R1-0/+42
Add device tree nodes for Tegra234 GPCDMA Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Adjust whitespace around '='Krzysztof Kozlowski1-1/+1
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Enable OPE on various platformsSameer Pujar6-0/+340
Enable OPE module usage on various Jetson platforms. This can be plugged into an audio path using ALSA mixer controls. Add audio-graph-port binding to use OPE device with generic audio-graph based sound card. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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