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2024-10-26arm64: dts: exynos8895: Add Multi Core Timer (MCT) nodeIvaylo Ivanov1-0/+20
MCT has one global timer and 8 CPU local timers. The global timer can generate 4 interrupts, and each local timer can generate an interrupt making 12 interrupts in total. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241023091734.538682-4-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-26arm64: dts: exynos8895: Add clock management unit nodesIvaylo Ivanov1-0/+85
Add clock management unit nodes for: - cmu_top, which provides muxes, divs and gates for other CMUs - cmu_peris, which provides clocks for GIC and MCT - cmu_fsys0, which provides clocks for USBDRD30 - cmu_fsys1, which provides clocks for MMC, UFS and PCIE - cmu_peric0, which provides clocks for UART_DBG, USI00 ~ USI03 - cmu_peric1, which provides clocks for SPI_CAM0/1, UART_BT, USI04 ~ USI13 Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241023091734.538682-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-17arm64: dts: exynos: Add initial support for Samsung Galaxy Note20 5G (c1s)Igor Belwon2-0/+116
Add initial support for the Samsung Galaxy Note20 5G (c1s/SM-N981B) phone. It was launched in 2020, and it's based on the Exynos 990 SoC. It has only one configuration with 8GB of RAM, albeit storage options may differ. This device tree adds support for the following: - SimpleFB - 8GB RAM - Buttons Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241016154747.64343-7-igor.belwon@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-17arm64: dts: exynos: Add initial support for the Exynos 990 SoCIgor Belwon2-0/+2446
The Exynos 990 SoC is an ARMv8 mobile SoC found in Samsung Galaxy N/S20 series phones (x1sxxx, c1sxxx). Add minimal support for this SoC, including: - All 8 cores via PSCI - ChipID - Generic timer. - Pinctrl The devices using this SoC suffer from the same issue as Exynos 8895 caused by the stock Samsung bootloader, as it doesn't configure CNTFRQ_EL0. Hence it's needed to hardcode the adequate frequency in the timer node, otherwise the kernel panics. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241016154747.64343-6-igor.belwon@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-10arm64: dts: exynosautov920: add peric1, misc and hsi0/1 clock DT nodesSunyeal Hong1-0/+50
Add cmu_peric1 for USI, I2C and I3C clocks respectively. Add cmu_misc for MISC, GIC and OTP clocks respectively. Add cmu_hsi0 for PCIE clocks respectively. Add cmu_hsi1 for USB and MMC clocks respectively. Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Link: https://lore.kernel.org/r/20241009042110.2379903-4-sunyeal.hong@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-02arm64: dts: exynos: Add initial support for Samsung Galaxy S8Ivaylo Ivanov2-0/+127
Samsung Galaxy S8 (SM-G950F), codenamed dreamlte, is a mobile phone from 2017. It features 4GB RAM, 64GB UFS 2.1, Exynos 8895 SoC and a 1440x2960 Super AMOLED display. This initial device tree enables SimpleFB, PSTORE and GPIO keys. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20240920154508.1618410-11-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-02arm64: dts: exynos: Add initial support for exynos8895 SoCIvaylo Ivanov2-0/+1345
Exynos 8895 SoC is an ARMv8 mobile SoC found in the Samsung Galaxy S8 (dreamlte), S8 Plus (dream2lte), Note 8 (greatlte) and the Meizu 15 Plus (m1891). Add minimal support for that SoC, including: - All 8 cores via PSCI - ChipID - Generic ARMV8 Timer - Enumarate all pinctrl nodes The devices using this SoC suffer from an issue caused by the stock Samsung bootloader, as it doesn't configure CNTFRQ_EL0. Hence it's needed to hardcode the adequate frequency in the timer node, otherwise the kernel panics. Further platform support will be added over time. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20240920154508.1618410-9-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-23arm64: dts: exynosautov920: add initial CMU clock nodes in ExynosAuto v920Sunyeal Hong1-13/+27
Add cmu_top, cmu_peric0 clock nodes and switch USI clocks instead of dummy fixed-rate-clock. Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Link: https://lore.kernel.org/r/20240821232652.1077701-3-sunyeal.hong@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-22arm64: dts: exynosautov9: Add dpum SysMMUKwanghoon Son1-0/+36
Add System Memory Management Unit(SysMMU) for dpum also called iommu. This sysmmu is version 7.4, which has same functionality as exynos850. DPUM has 4 dma channel, each channel is mapped to one iommu. Signed-off-by: Kwanghoon Son <k.son@samsung.com> Link: https://lore.kernel.org/r/20240819-add_sysmmu-v1-1-799c0f3f607f@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-11arm64: dts: exynosautov9: add dpum clock DT nodesKwanghoon Son1-0/+10
Add dpum clock for sysmmu, dpu. Signed-off-by: Kwanghoon Son <k.son@samsung.com> Link: https://lore.kernel.org/r/20240809-clk_dpum-v3-2-359decc30fe2@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-07-29arm64: dts: exynos: gs101: add syscon-poweroff and syscon-reboot nodesPeter Griffin1-0/+15
Reboot of gs101 SoC can be handled by setting the bit(SWRESET_SYSTEM[1]) of SYSTEM_CONFIGURATION register(PMU + 0x3a00). Poweroff of gs101 SoC can be handled by setting bit(DATA[8]) of PAD_CTRL_PWR_HOLD register (PMU + 0x3e9c). Tested using "reboot" and "poweroff -p" commands. Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20240628223506.1237523-3-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-07-29arm64: dts: exynos: exynos7885-jackpotlte: Correct RAM amount to 4GBDavid Virag1-1/+1
All known jackpotlte variants have 4GB of RAM, let's use it all. RAM was set to 3GB from a mistake in the vendor provided DTS file. Fixes: 06874015327b ("arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC") Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240713180607.147942-3-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-07-01arm64: dts: exynos850: Enable TRNGSam Protsenko1-0/+8
Add True Random Number Generator (TRNG) node to Exynos850 SoC dtsi. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240618204523.9563-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-06-20arm64: dts: exynos: gs101-oriole: add placeholder regulators for USB phyAndré Draszik1-0/+7
The USB phy requires various power supplies to work. While we don't have a PMIC driver yet, the supplies should still be added to the DT. Add some placeholders, which will be replaced with the real ones once we implement PMIC. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240618-gs101-usb-regulators-in-dt-v3-1-6a749207052e@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-06-15arm64: dts: exynos: gs101: reorder properties as per guidelinesAndré Draszik2-12/+12
* 'interrupts' & 'cpus' & 'clocks' are standard/common properties as per the Devicetree Sources (DTS) Coding Style and therefore should be sorted alphabetically within the standard/common section * vendor properties should be last * reg / ranges should be 2nd/3rd (after compatible) * status should be last Do so. Note: I've left the cpus{} node untouched to keep the grouping of relatedd properties. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240611-gs101-dts-cleanup-v1-1-877358cd6536@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-05-03arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrlAndré Draszik1-0/+9
The pinctrl instances hsi1, gsactrl, and gsacore need a clock for register access to work. Since we haven't implemented the relevant CMUs for the clocks required by these instances just add empty clocks for now so as to make the DT pass the validation checks. Once the clocks are implmented in the gs101 clock driver, these should be updated then. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-4-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-05-03arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2André Draszik1-0/+2
This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-3-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-05-03arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01]André Draszik1-0/+4
This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-2-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-05-03arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) aliveAndré Draszik1-0/+4
This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-1-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-30arm64: dts: exynos: gs101: enable ufs, phy on oriole & define ufs regulatorPeter Griffin1-0/+18
Enable ufs & ufs phy nodes for Oriole. Also define the ufs regulator node. ufs regulator is a stub until full s2mpg11 slave pmic support is added. The gpio defined is for the BOOTLD0 (gs101) signal connected to UFS_EN(s2mpg11) gpio enabled voltage rail for UFS. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240430141445.2688499-4-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-30arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodesPeter Griffin1-0/+36
Add the ufs controller node and phy node for gs101. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240430141445.2688499-3-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-30arm64: dts: exynos: gs101: Add the hsi2 sysreg nodePeter Griffin1-0/+6
This has some configuration bits such as sharability that are required by UFS. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240430141445.2688499-2-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-29arm64: dts: exynos: gs101-oriole: enable USB on this boardAndré Draszik1-0/+24
Pixel 6 (Oriole) has a USB-C connector that can act as host or device. The USB role is detected dynamically using a MAX77759 TCPCI controller, but since there is no driver for the MAX77759, the role is defaulted to peripheral, without any endpoints / ports. This allows Oriole to be configured as a gadget, e.g. using configfs. As PMIC regulators are not implemented yet, we rely on USB LDOs being enabled by the bootloader. A placeholder regulator is used for now. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-dts-gs101-v2-2-7c1797c9db80@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-29arm64: dts: exynos: gs101: add USB & USB-phy nodesAndré Draszik1-0/+41
Add the USB 3.1 Dual Role Device (DRD) controller and USB-PHY nodes for Google Tensor GS101. The USB 3.1 DRD controller has the following features: * compliant with both USB device 3.1 and USB device 2.0 standards * compliant with USB host 3.1 and USB host 2.0 standards * supports USB device 3.1 and USB device 2.0 interfaces * supports USB host 3.1 and USB host 2.0 interfaces * full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device 2.0 interface * super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface * super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface * single USB port which can be used for USB 3.1 or USB 2.0 * on-chip USB PHY transceiver * DWC3 compatible * supports up to 16 bi-directional endpoints * compliant with xHCI 1.1 specification Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-dts-gs101-v2-1-7c1797c9db80@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-29arm64: dts: exynos: gs101: enable cmu-hsi2 clock controllerPeter Griffin1-0/+12
Enable the cmu_hsi2 clock management unit. It feeds some of the high speed interfaces such as PCIe and UFS. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240429-hsi0-gs101-v3-2-f233be0a2455@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-29arm64: dts: exynos: gs101: enable cmu-hsi0 clock controllerAndré Draszik1-0/+14
Enable the cmu-hsi0 clock controller. It feeds USB. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240426-hsi0-gs101-v2-2-2157da8b63e3@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-28arm64: dts: exynos: gs101: define all PERIC USI nodesTudor Ambarus1-0/+769
Universal Serial Interface (USI) supports three types of serial interface such as UART, SPI and I2C. Each protocol works independently. USI can be configured to work as one of these protocols. Define all the USI nodes from the PERIC blocks (USI0-14), in all their possible configurations. These blocks have the TX/RX FIFO depth of 64 bytes. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240326151301.348932-6-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-28arm64: dts: exynos: gs101: join lines close to 80 charsTudor Ambarus1-8/+4
These lines fit 81 characters, which is pretty close to 80. Join the lines for better readability. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240326151301.348932-5-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-28arm64: dts: exynos: gs101: move pinctrl-* properties after clocksTudor Ambarus1-4/+4
Move the pinctrl-* properties after clocks so that we keep alphabetic order and align with the other similar definitions. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240326151301.348932-4-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-28arm64: dts: exynos: gs101: move serial_0 pinctrl-0/names to dtsiTudor Ambarus2-2/+2
The pinctrl nodes are coming from the shared gs101-pinctrl.dtsi, thus the pinctrl-0/names shall stay in dtsi. Move them. Reviewed-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240326151301.348932-3-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-28arm64: dts: exynos: gs101: reorder pinctrl-* propertiesAndré Draszik2-3/+3
The Preferred order for these is pinctrl-0 pinctrl-names. Update the DTSI & DTS accordingly. Signed-off-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240326151301.348932-2-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-26arm64: dts: exynos850: Add CPU clocksSam Protsenko1-0/+26
Define CPU cluster 0 and CPU cluster 1 CMUs, which generate CPU clocks, and add corresponding CPU clocks to CPU nodes. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240301015118.30072-3-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-25arm64: dts: exynosautov9: specify the SPI FIFO depthTudor Ambarus1-0/+12
Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. There are no SPI aliases defined, thus the FIFO depth was determined by matching the FIFO depth of the I2C node of the same USI parent. No functional change expected. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240216140449.2564625-7-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-03-25arm64: dts: exynos5433: specify the SPI FIFO depthTudor Ambarus1-0/+5
Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depthj Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. The FIFO depth were determined based on the SPI aliases that are defined in exynos5433-tm2-common.dtsi: spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; spi3 = &spi_3; spi4 = &spi_4; spi-s3c64xx.c driver defines the following fifo_lvl_mask for the "samsung,exynos5433-spi" compatible: .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, Thus spi{0, 4} were considered having 256 byte FIFO depths, and spi{1, 2, 3} having 64 byte FIFO depths. Update device tree with these FIFO depths. No functional change expected. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240216140449.2564625-6-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-29Merge tag 'samsung-dt64-6.9' of ↵Arnd Bergmann4-20/+201
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM64 changes for v6.9 Mostly work around Google GS101 SoC and Pixel phone (Oriole) adding support for: 1. Multi Core Timer (MCT) clocksource. 2. Several clock controllers (DTS and DT bindings) and use new clocks in several other device nodes. 3. More serial-interface instances: USI8 and USI12 with I2C. Exynos850: 1. SPI and DMA controllers (PL330). * tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: fsd: Add fifosize for UART in Device Tree arm64: dts: exynos: gs101: minor whitespace cleanup arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole arm64: dts: exynos: gs101: define USI12 with I2C configuration arm64: dts: exynos: gs101: enable cmu-peric1 clock controller dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit arm64: dts: exynos: Add SPI nodes for Exynos850 arm64: dts: exynos: Add PDMA node for Exynos850 arm64: dts: exynos: gs101: use correct clocks for usi_uart arm64: dts: exynos: gs101: use correct clocks for usi8 arm64: dts: exynos: gs101: sysreg_peric0 needs a clock arm64: dts: exynos: gs101: enable eeprom on gs101-oriole arm64: dts: exynos: gs101: define USI8 with I2C configuration arm64: dts: exynos: gs101: update USI UART to use peric0 clocks arm64: dts: exynos: gs101: enable cmu-peric0 clock controller arm64: dts: exynos: gs101: remove reg-io-width from serial arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node dt-bindings: clock: exynos850: Add PDMA clocks dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit Link: https://lore.kernel.org/r/20240218182141.31213-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-02-12arm64: dts: exynos: gs101: minor whitespace cleanupKrzysztof Kozlowski2-9/+9
The DTS code coding style expects exactly one space before '{' and around '=' characters. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240208105243.128875-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-08arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-orioleAndré Draszik1-0/+10
This bus has three USB-related devices attached to it: 0x25: Maxim 77759 Type-C port controller 0x35: Maxim 20339EWB Surge protection IC 0x36: Maxim 77759 Fuel gauge 0x57: NXP PCA9468 Battery charger 0x66: Maxim 77759 PMIC 0x69: Maxim 77759 Charger where the Maxim 77759 has multiple i2c slave addresses. These don't have (upstream) Linux drivers yet, but nevertheless we can enable the bus so as to allow working on them (and to make i2cdetect / i2cdump / etc. work). Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240201161258.1013664-8-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-08arm64: dts: exynos: gs101: define USI12 with I2C configurationAndré Draszik1-0/+29
On the gs101-oriole board, i2c bus 12 has various USB-related controllers attached to it. Note the selection of the USI protocol is intentionally left for the board dts file. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240201161258.1013664-7-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-08arm64: dts: exynos: gs101: enable cmu-peric1 clock controllerAndré Draszik1-0/+11
Enable the cmu-peric1 clock controller. It feeds additional USI, I3C and PWM interfaces / busses. Note that &sysreg_peric1 needs a clock to be able to access its registers and now that Linux knows about this clock, we need to add it in this commit as well so as to keep &sysreg_peric1 working, so that the clock can be enabled as and when needed. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240201161258.1013664-6-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-06arm64: dts: exynos: Add SPI nodes for Exynos850Sam Protsenko1-0/+54
Some USI blocks can be configured as SPI controllers. Add corresponding SPI nodes to Exynos850 SoC device tree. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240201183025.14566-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-01arm64: dts: exynos: Add PDMA node for Exynos850Sam Protsenko1-0/+10
Enable PDMA node. It's needed for multiple peripheral modules, like SPI. Use "arm,pl330-broken-no-flushp" quirk, as otherwise SPI transfers in DMA mode often fail with error like this: I/O Error: rx-1 tx-1 rx-f tx-f len-786 dma-1 res-(-5) Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240125013858.3986-3-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-01arm64: dts: exynos: gs101: use correct clocks for usi_uartAndré Draszik1-2/+2
Wrong pclk clocks have been used in this usi_uart instance here. For USI and UART, we need the ipclk and pclk, where pclk is the bus clock. Without it, nothing can work. It is unclear what exactly is using USI0_UART_CLK, but it is not required for the IP to be operational at this stage, while pclk is. This also brings the DT in line with the clock names expected by the usi and uart drivers. Fixes: d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Tested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240130093812.1746512-5-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-01arm64: dts: exynos: gs101: use correct clocks for usi8André Draszik1-2/+2
Wrong pclk clocks have been used in this usi8 instance here. For USI and I2C, we need the ipclk and pclk, where pclk is the bus clock. Without it, nothing can work. It is unclear what exactly is using USI8_USI_CLK, but it is not required for the IP to be operational at this stage, while pclk is. This also brings the DT in line with the clock names expected by the usi and i2c drivers. Fixes: 6d44d1a1fb62 ("arm64: dts: exynos: gs101: define USI8 with I2C configuration") Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Tested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240130093812.1746512-4-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-26arm64: dts: exynos: gs101: sysreg_peric0 needs a clockAndré Draszik1-0/+1
Without the clock running, we can not access its registers, and now that we have it, we should add it here so that it gets enabled as and when needed. Update the DTSI accordingly. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240126115517.1751971-2-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23arm64: dts: exynos: gs101: enable eeprom on gs101-orioleTudor Ambarus1-0/+14
Enable the eeprom found on the battery connector. The selection of the USI protocol is done in the board dts file because the USI CONFIG register comes with a 0x0 reset value, meaning that USI8 does not have a default protocol (I2C, SPI, UART) at reset. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240119111132.1290455-9-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23arm64: dts: exynos: gs101: define USI8 with I2C configurationTudor Ambarus1-0/+29
USI8 I2C is used to communicate with an eeprom found on the battery connector. Define USI8 in I2C configuration. USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the selection of the protocol is intentionally left for the board dts file. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240119111132.1290455-8-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23arm64: dts: exynos: gs101: update USI UART to use peric0 clocksTudor Ambarus1-10/+4
Get rid of the dummy clock and start using the cmu_peric0 clocks for the usi_uart and serial_0 nodes. Tested the serial at 115200, 1000000 and 3000000 baudrates, everthing went fine. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240119111132.1290455-7-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23arm64: dts: exynos: gs101: enable cmu-peric0 clock controllerTudor Ambarus1-0/+10
Enable the cmu-peric0 clock controller. It feeds USI and I3c. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240119111132.1290455-6-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23arm64: dts: exynos: gs101: remove reg-io-width from serialTudor Ambarus1-1/+0
Remove the reg-io-width property in order to comply with the bindings. The entire bus (PERIC) on which the GS101 serial resides only allows 32-bit register accesses. The reg-io-width dt property is disallowed for the "google,gs101-uart" compatible and instead the iotype is inferred from the compatible. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240119111132.1290455-5-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-01-23arm64: dts: exynos: gs101: define Multi Core Timer (MCT) nodePeter Griffin1-0/+20
MCT has one global timer and 8 CPU local timers. The global timer can generate 4 interrupts, and each local timer can generate an interrupt making 12 interrupts in total. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20231222165355.1462740-4-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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