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2022-11-16arm64: dts: allwinner: h6: Add IOMMU reference to Hantro G2Chen-Yu Tsai1-0/+1
The Hantro G2 video decoder block sits behind the IOMMU. Without a reference for the system to properly configure the IOMMU, it will fault and cause the video decoder to fail. Add a proper reference to the IOMMU port. The master ID is taken from the IOMMU fault error message on Linux, and the number seems to match the order in the user manual's IOMMU diagram. Fixes: 0baddea60e8d ("arm64: dts: allwinner: h6: Add Hantro G2 node") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221115090644.3602573-3-wenst@chromium.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-09-08arm64: dts: allwinner: h6: Add cooling map for GPUClément Péron1-2/+49
Add a simple cooling map for the GPU. This cooling map come from the vendor kernel 4.9 with a 2°C hysteresis added. Signed-off-by: Clément Péron <peron.clem@gmail.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220906153034.153321-3-peron.clem@gmail.com
2022-06-13arm64: dts: allwinner: Use constants for RTC clock indexesSamuel Holland1-5/+7
The binding header provides descriptive names for the RTC clock indexes, since the indexes were arbitrarily chosen by the binding, not by the hardware. Let's use the names, so the meaning is clearer. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220607012438.18183-2-samuel@sholland.org
2021-12-16arm64: dts: allwinner: h6: Add Hantro G2 nodeJernej Skrabec1-0/+9
H6 SoC has a second VPU, dedicated to VP9 decoding. It's a slightly older design, though. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211129182633.480021-10-jernej.skrabec@gmail.com
2021-09-13arm64: dts: allwinner: h6: Fix de3 parent clocks orderingMaxime Ripard1-4/+4
While it doesn't really matter from a functional point of view in this driver's case, it's usually a good practice to list the clocks in a driver in the same driver across all its users. The H6 is using the inverse order than all the other users, so let's make it consistent. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-49-maxime@cerno.tech
2021-05-11arm64: dts: allwinner: Add sun4i MMIO timer nodesSamuel Holland1-0/+9
For a CPU to enter an idle state, some timer must be available to trigger an IRQ and wake it back up. The local ARM architectural timer is not sufficient, because that timer stops when the CPU is powered down. The ARM architectural timer from some other CPU can be used, but doing so prevents that other CPU from entering an idle state. For all CPUs to power down at the same time, Linux needs a timer which is not tied to any CPU. Hook up the "sun4i" timer so it can be used for this purpose. It runs at 24 MHz, which balances resolution and power consumption. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210322044707.19479-5-samuel@sholland.org
2021-04-26Merge tag 'arm-dt-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-3/+5
Pull ARM devicetree updates from Arnd Bergmann: "There are six new SoCs added this time. Apple M1 and Nuvoton WPCM450 have separate branches because they are new SoC families that require changes outside of device tree files. The other four are variations of already supported chips and get merged through this branch: - STMicroelectronics STM32H750 is one of many variants of STM32 microcontrollers based on the Cortex-M7 core. This is particularly notable since we rarely add support for new MMU-less chips these days. In this case, the board that gets added along with the platform is not a SoC reference platform but the "Art Pi" (https://art-pi.gitee.io/website/) machine that was originally design for the RT-Thread RTOS. - NXP i.MX8QuadMax is a variant of the growing i.MX8 embedded/industrial SoC family, using two Cortex-A72 and four Cortex-A53 cores. It gets added along with its reference board, the "NXP i.MX8QuadMax Multisensory Enablement Kit". - Qualcomm SC7280 is a Laptop SoC following the SC7180 (Snapdragon 7c) that is used in some Chromebooks and Windows laptops. Only a reference board is added for the moment. - TI AM64x Sita4ra is a new version of the K3 SoC family for industrial control, motor control, remote IO, IoT gateway etc., similar to the older AM65x family. Two reference machines are added alongside. Among the newly added machines, there is a very clear skew towards 64-bit machines now, with 12 32-bit machines compared to 23 64-bit machines. The full list sorted by SoC is: - ASpeed AST2500 BMC: ASRock E3C246D4I Xeon server board - Allwinner A10: Topwise A721 Tablet - Amlogic GXL: MeCool KII TV box - Amlogic GXM: Mecool KIII, Minix Neo U9-H TV boxes - Broadcom BCM4908: TP-Link Archer C2300 V1 router - MStar SSD202D: M5Stack UnitV2 camera - Marvell Armada 38x: ATL-x530 ethernet switch - Mediatek MT8183 Chromebooks: Lenovo 10e, Acer Spin 311, Asus Flip CM3, Asus Detachable CM3 - Mediatek MT8516/MT8183: OLogic Pumpkin Board - NXP i.MX7: reMarkable Tablet - NXP i.MX8M: Kontron pitx-imx8m, Engicam i.Core MX8M Mini - Nuvoton NPCM730: Quanta GBS BMC - Qualcomm X55: Telit FN980 TLB SoM, Thundercomm TurboX T55 SoM - Qualcomm MSM8998: OnePlus 5/5T phones - Qualcomm SM8350: Snapdragon 888 Mobile Hardware Development Kit - Rockchip RK3399: NanoPi R4S board - STM32MP1: Engicam MicroGEA STM32MP1 MicroDev 2.0 and SOM, EDIMM2.2 Starter Kit, Carrier, SOM - TI AM65: Siemens SIMATIC IOT2050 gateway There is notable work going into extending already supported machines and SoCs: - ASpeed AST2500 - Allwinner A23, A83t, A31, A64, H6 - Amlogic G12B - Broadcom BCM4908 - Marvell Armada 7K/8K/CN91xx - Mediatek MT6589, MT7622, MT8173, MT8183, MT8195 - NXP i.MX8Q, i.MX8MM, i.MX8MP - Qualcomm MSM8916, SC7180, SDM845, SDX55, SM8350 - Renesas R-Car M3, V3U - Rockchip RK3328, RK3399 - STEricsson U8500 - STMicroelectronics STM32MP141 - Samsung Exynos 4412 - TI K3-AM65, K3-J7200 - TI OMAP3 Among the treewide cleanups and bug fixes, two parts stand out: - There are a number of cleanups for issues pointed out by 'make dtbs_check' this time, and I expect more to come in the future as we increasingly check for regressions. - After a change to the MMC subsystem that can lead to unpredictable device numbers, several platforms add 'aliases' properties for these to give each MMC controller a fixed number" * tag 'arm-dt-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (516 commits) dt-bindings: mali-bifrost: add dma-coherent arm64: dts: amlogic: misc DT schema fixups arm64: dts: qcom: sc7180: Update iommu property for simultaneous playback arm64: dts: qcom: sc7180: pompom: Add "dmic_clk_en" + sound model arm64: dts: qcom: sc7180: coachz: Add "dmic_clk_en" ARM: dts: mstar: Add a dts for M5Stack UnitV2 dt-bindings: arm: mstar: Add compatible for M5Stack UnitV2 dt-bindings: vendor-prefixes: Add vendor prefix for M5Stack arm64: dts: mt8183: fix dtbs_check warning arm64: dts: mt8183-pumpkin: fix dtbs_check warning ARM: dts: aspeed: tiogapass: add hotplug controller ARM: dts: aspeed: amd-ethanolx: Enable all used I2C busses ARM: dts: aspeed: Rainier: Update to pass 2 hardware ARM: dts: aspeed: Rainier 1S4U: Fix fan nodes ARM: dts: aspeed: Rainier: Fix humidity sensor bus address ARM: dts: aspeed: Rainier: Fix PCA9552 on bus 8 ARM: dts: qcom: sdx55: add IPA information ARM: dts: qcom: sdx55: Add basic devicetree support for Thundercomm T55 dt-bindings: arm: qcom: Add binding for Thundercomm T55 kit ARM: dts: qcom: sdx55: Add basic devicetree support for Telit FN980 TLB ...
2021-04-07arm64: dts: allwinner: h6: Switch to macros for RSB clock/reset indicesChen-Yu Tsai1-2/+2
The macros for the clock and reset indices for the RSB hardware block were replaced with raw numbers when the RSB controller node was added. This was done to avoid cross-tree dependencies. Now that both the clk and DT changes have been merged, we can switch back to using the macros. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2021-03-06arm64: dts: allwinner: Move wakeup-capable IRQs to r_intcSamuel Holland1-0/+3
All IRQs that can be used to wake up the system must be routed through r_intc, so they are visible to firmware while the system is suspended. In addition to the external NMI input, which is already routed through r_intc, these include PIO and R_PIO (gpio-keys), the LRADC, and the RTC. Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2021-03-06arm64: dts: allwinner: Use the new r_intc bindingSamuel Holland1-3/+2
The binding of R_INTC was updated to allow specifying interrupts other than the external NMI, since routing those interrupts through the R_INTC driver allows using them for wakeup. Update the device trees to use the new binding. Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2021-01-18arm64: dts: allwinner: h6: Add RSB controller nodeSamuel Holland1-0/+19
The H6 SoC contains an undocumented but fully functional RSB controller. Add support for it. The MMIO register address matches other SoCs of the same generation, and the IRQ matches a hole in the documented IRQ list. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Maxime Ripard <mripard@kernel.org> [wens@csie.org: Use raw numbers instead of macros for clock/reset index] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2021-01-14arm64: dts: allwinner: H6: Allow up to 150 MHz MMC bus frequencyAndre Przywara1-0/+3
The H6 manual explicitly lists a frequency limit of 150 MHz for the bus frequency of the MMC controllers. So far we had no explicit limits in the DT, which limited eMMC to the spec defined frequencies, or whatever the driver defines (both Linux and FreeBSD use 52 MHz here). Put those maximum frequencies in the SoC .dtsi, to allow higher speed modes (which still would need to be explicitly enabled, per board). Tested with an eMMC using HS-200 on a Pine H64. Running at the spec'ed 200 MHz indeed fails with I/O errors, but 150 MHz seems to work stably. Fixes: 8f54bd1595b3 ("arm64: allwinner: h6: add device tree nodes for MMC controllers") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210113152630.28810-6-andre.przywara@arm.com
2021-01-14arm64: dts: allwinner: H6: properly connect USB PHY to port 0Andre Przywara1-0/+4
In recent Allwinner SoCs the first USB host controller (HCI0) shares the first PHY with the MUSB controller. Probably to make this sharing work, we were avoiding to declare this in the DT. This has two shortcomings: - U-Boot (which uses the same .dts) cannot use this port in host mode without a PHY linked, so we were loosing one USB port there. - It requires the MUSB driver to be enabled and loaded, although we don't actually use it. To avoid those issues, let's add this PHY link to the H6 .dtsi file. After all PHY port 0 *is* connected to HCI0, so we should describe it as this. This makes it work in U-Boot, also improves compatiblity when no MUSB driver is loaded (for instance in distribution installers). Fixes: eabb3d424b6d ("arm64: dts: allwinner: h6: add USB2-related device nodes") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210113152630.28810-3-andre.przywara@arm.com
2020-11-02arm64: dts: allwinner: h6: Add I2S1 nodeJernej Skrabec1-0/+13
Add Allwinner H6 I2S1 node connected to HDMI interface. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20201030144648.397824-12-peron.clem@gmail.com
2020-10-26arm64: dts: allwinner: h6: Harmonize DWC USB3 DT nodes nameSerge Semin1-1/+1
In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201020115959.2658-25-Sergey.Semin@baikalelectronics.ru
2020-08-18arm64: dts: allwinner: Mark timer as stopped in suspendSamuel Holland1-0/+1
When possible, system firmware on 64-bit Allwinner platforms disables OSC24M during system suspend. Since this oscillator is the clock source for the ARM architectural timer, this causes the timer to stop counting. Therefore, the ARM architectural timer must not be marked as NONSTOP on these platforms, or the time will be wrong after system resume. Adding the arm,no-tick-in-suspend property forces the kernel to ignore the ARM architectural timer when calculating sleeptime; it falls back to reading the RTC. Note that this only affects deep suspend, not s2idle. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200809021822.5285-1-samuel@sholland.org
2020-07-16arm64: dts: allwinner: h6: Fix Cedrus IOMMU usageMaxime Ripard1-0/+1
Now that the IOMMU driver has been introduced, it prevents any access from a DMA master going through it that hasn't properly mapped the pages, and that link is set up through the iommus property. Unfortunately we forgot to add that property to the video engine node when adding the IOMMU node, so now any DMA access is broken. Fixes: b3a0a2f910c7 ("arm64: dts: allwinner: h6: Add IOMMU") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200628180804.79026-1-maxime@cerno.tech
2020-05-15arm64: dts: allwinner: h6: Add IOMMUMaxime Ripard1-0/+10
Now that we have a driver for the IOMMU, let's start using it. Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-04-23arm64: dts: allwinner: h6: Add CPU Operating Performance Points tableOndrej Jirman1-0/+4
Add an Operating Performance Points table for the CPU cores to enable Dynamic Voltage & Frequency Scaling on the H6. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-04-23arm64: dts: allwinner: h6: Add thermal trip points/cooling mapOndrej Jirman1-0/+28
This enables passive cooling by down-regulating CPU voltage and frequency. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-04-20arm64: dts: allwinner: h6: Add clock to CPU coresYangtao Li1-0/+8
The ARM CPU cores are fed by the CPU clock from the CCU. Add a reference to the clock for each CPU core, along with the clock transition latency. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-04-14arm64: dts: allwinner: h6: Add msgbox nodeSamuel Holland1-0/+10
The H6 SoC contains a message box that can be used to send messages and interrupts back and forth between the ARM application CPUs and the ARISC coprocessor. Add a device tree node for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-03-09arm64: dts: allwinner: h6: Move ext. oscillator to board DTsJernej Skrabec1-8/+0
It turns out that not all H6 boards have external 32kHz oscillator. Currently the only one known such H6 board is Tanix TX6. Move external oscillator node from common H6 dtsi to board specific dts files where present. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-02-25arm64: dts: allwinner: h6: Fix PMU compatibleMaxime Ripard1-2/+1
The commit 7aa9b9eb7d6a ("arm64: dts: allwinner: H6: Add PMU mode") introduced support for the PMU found on the Allwinner H6. However, the binding only allows for a single compatible, while the patch was adding two. Make sure we follow the binding. Fixes: 7aa9b9eb7d6a ("arm64: dts: allwinner: H6: Add PMU mode") Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-02-10arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxesAndre Przywara1-0/+55
The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, but with the added capability of 3-wire and 4-wire operation modes. For now the driver does not support those, but the SPI registers are fully backwards-compatible, just adding bits and registers which were formerly reserved. So we can use the existing driver in "legacy" SPI modes, for instance to access the SPI NOR flash soldered on the PineH64 board. We use an H6 specific compatible string in addition to the existing H3 string, so when the driver later gains QSPI support, it should work automatically without any DT changes. Tested by accessing the SPI flash on a Pine H64 board (SPI0), also connecting another SPI flash to the SPI1 header pins. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-27arm64: dts: allwinner: h6: Add thermal sensor and thermal zonesOndrej Jirman1-0/+33
There are two sensors, one for CPU, one for GPU. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-16arm64: dts: allwinner: unify header comment styleClément Péron1-3/+1
Allwinner device tree files used different comment style for copyright notice. Update this to keep a coherency. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-11arm64: dts: allwiner: Fix typo in dual licensed SPDX identifierClément Péron1-1/+1
With dual licensed SPDX identifier the "OR" should be uppercase. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-11arm64: dts: allwinner: h6: Add PWM nodeJernej Skrabec1-0/+10
Allwinner H6 PWM is similar to that in A20 except that it has additional bus clock and reset line. Note that first PWM channel is connected to output pin and second channel is used internally, as a clock source to AC200 co-packaged chip. This means that any combination of these two channels can be used and thus it doesn't make sense to add pinctrl nodes at this point. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-10arm64: dts: allwinner: H6: Add PMU modeAndre Przywara1-0/+10
Add the Performance Monitoring Unit (PMU) device tree node to the H6 .dtsi, which tells DT users which interrupts are triggered by PMU overflow events on each core. The numbers come from the manual and have been checked in U-Boot and with perf in Linux. Tested with perf record and taskset on a Pine H64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-05Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-1/+65
Pull ARM Device-tree updates from Olof Johansson: "As always, the bulk of updates. Some of the news this cycle: New SoC descriptions: - Broadcom BCM2711 - Amlogic Meson A1 and G12 - Freescale S32V234 - Marvell Armada AP807/AP807-quad and CP115 - Realtek RTD1293 and RTD1296 - Rockchip RK3308 New boards and platforms: - Allwinner: NanoPi Duo2 - Amlogic: Ugoos am6 - Atmel at91: Overkiz Kizbox2/4 - Broadcom: RPi4, Luxul XWC-2000 - Marvell: New Espressobin flavor - NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and OPOS6ULDev - Renesas: Salvator-XS - Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (653 commits) ARM: dts: logicpd-torpedo: Disable USB Host arm: dts: mt6323: add keys, power-controller, rtc and codec arm64: dts: mt8183: add systimer0 device node dt-bindings: mediatek: update bindings for MT8183 systimer arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board. arm64: dts: rockchip: Add Beelink A1 dt-bindings: ARM: rockchip: Add Beelink A1 arm64: dts: rockchip: Add RK3328 audio pipelines arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports arm64: dts: ti: k3-j721e-main: add USB controller nodes ARM: dts: aspeed-g6: Add timer description ARM: dts: aspeed: ast2600evb: Enable i2c buses ARM: dts: at91: add a dts and dtsi file for kizbox2 based boards dt-bindings: arm: at91: Document Kizbox2-2 board binding arm64: dts: meson-gx: fix i2c compatible arm64: dts: meson-gx: cec node should be disabled by default arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible arm64: dts: meson-gxm: fix gpu irq order arm64: dts: meson-g12a: fix gpu irq order ...
2019-11-05arm64: dts: allwinner: h6: Remove useless reset nameMaxime Ripard1-1/+0
The TCON TOP node in the H6 DTSI has a reset name that isn't described in the binding. Remove it. Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-05arm64: dts: allwinner: h6: add USB3 device nodesIcenowy Zheng1-0/+32
Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and a custom PHY. Add device tree nodes for them. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-01arm64: dts: allwinner: sun50i: Add Crypto Engine node on H6Corentin Labbe1-0/+9
The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. This patch enables the Crypto Engine on the Allwinner H6 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-10-31arm64: dts: allwinner: Add ARM Mali GPU node for H6Clément Péron1-0/+14
Add the mali gpu node to the H6 device-tree. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-10-08arm64: dts: allwinner: h6: Add pin configs for uart1Ondrej Jirman1-0/+10
Orange Pi 3 uses UART1 for bluetooth. Add pinconfigs so that we can use them. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Maxime Ripard <mripard@kernel.org>
2019-10-04ARM: dts: sunxi: Revert phy-names removal for ECHI and OHCIMaxime Ripard1-0/+2
This reverts commits 3d109bdca981 ("ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI"), 0a3df8bb6dad ("ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI") and 3c7ab90aaa28 ("arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCI"). It turns out that while the USB bindings were not mentionning it, the PHY client bindings were mandating that phy-names is set when phys is. Let's add it back. Fixes: 3d109bdca981 ("ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI") Fixes: 0a3df8bb6dad ("ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI") Fixes: 3c7ab90aaa28 ("arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCI") Reported-by: Emmanuel Vadot <manu@bidouilliste.com> Signed-off-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20191002112651.100504-1-mripard@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-08-23ARM: dts: sunxi: Add missing watchdog clocksMaxime Ripard1-0/+2
The watchdog has a clock on all our SoCs, but it wasn't always listed. Add it to the devicetree where it's missing. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-08-23arm64: dts: allwinner: h6: Add support for RTC and fix the clock treeOndrej Jirman1-14/+16
This patch adds RTC node and fixes the clock properties and nodes to reflect the real clock tree. The device nodes for the internal oscillator and osc32k are removed, as these clocks are now provided by the RTC device. Clock references are fixed accordingly, too. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-08-23arm64: allwinner: h6: add I2C nodesBhushan Shah1-1/+59
Add device-tree nodes for i2c0 to i2c2, and also add relevant pinctrl nodes. Suggested-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Bhushan Shah <bshah@kde.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-08-23arm64: dts: allwinner: Add SPDIF node for Allwinner H6Clément Péron1-0/+20
The Allwinner H6 has a SPDIF controller called OWA (One Wire Audio). Only one pinmuxing is available so set it as default. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-24arm64: dts: allwinner: h6: Add IR receiver nodeClément Péron1-0/+19
Allwinner H6 IR is similar to A31 and can use same driver. Add support for it. Signed-off-by: Clément Péron <peron.clem@gmail.com> Acked-by: Sean Young <sean@mess.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-23ARM: dts: sunxi: Fix the HDMI PHY nameMaxime Ripard1-1/+1
Even though the binding mentions that the PHY name must be "phy", it turns out that all our DTs had "hdmi-phy" instead. The code doesn't care about the phy-names property, so we can just change our DTs to match the binding, without any side effect. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-22arm64: dts: allwinner: h6: Fix SID node nameMaxime Ripard1-1/+1
The SID node one the H6 doesn't have a standard node name. Switch to the one we use for the other SoCs. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-06-12arm64: dts: allwinner: h6: Add DMA nodeJernej Skrabec1-0/+12
H6 has DMA controller which supports 16 channels. Add a node for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-05-24arm64: dts: allwinner: h6: add r_watchog nodeClément Péron1-0/+7
Allwinner H6 has a r_watchdog similar to A64. Declare it in the device-tree. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-05-24arm64: dts: allwinner: h6: add watchdog nodeClément Péron1-0/+9
Allwinner H6 has a watchog node which seems broken on some boards. Test has been performed on several boards. Chen-Yu Tsai boards: Pine H64 - H6448BA 7782 => OK OrangePi Lite 2 - H8068BA 61C2 => KO Martin Ayotte boards: Pine H64 - H8069BA 6892 => OK OrangePi 3 - HA047BA 69W2 => KO OrangePi One Plus - H7310BA 6842 => KO OrangePi Lite2 - H6448BA 6662 => KO Clément Péron board: Beelink GS1 - H7309BA 6842 => KO As it seems not fixable for now, declare the node but leave it disable with a comment. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17arm64: dts: allwinner: Fix DE2 bus node nameMaxime Ripard1-1/+1
According to the device tree specification, any bus should have a 'bus' node name. Since it isn't the case for us on the DE2 bus, fix that. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCIMaxime Ripard1-2/+0
Neither the OHCI or EHCI bindings are using the phy-names property, so we can just drop it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-15arm64: dts: allwinner: h6: Add MMC1 pinsOndrej Jirman1-0/+11
MMC1 is used on some H6 boards we want to support. Typical use is 4-bit SDIO interface with a WiFi chip. Add pin definitions for this use case. As this is the only possible configration for mmc1, make it the default one, too. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-16 16:52:37 +0300