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Pull ARM updates from Russell King:
- improve ARM implementation of pfn_valid()
- various sparse fixes
- spelling fixes
- add further ARMv8 debug architecture versions
- clang fix for decompressor
- update to generic vDSO
- remove Brahma-B53 from spectre hardening
- initialise broadcast hrtimer device
- use correct nm executable in decompressor
- remove old mcount et.al.
* tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (26 commits)
ARM: 8940/1: ftrace: remove mcount(),ftrace_caller_old() and ftrace_call_old()
ARM: 8939/1: kbuild: use correct nm executable
ARM: 8938/1: kernel: initialize broadcast hrtimer based clock event device
ARM: 8937/1: spectre-v2: remove Brahma-B53 from hardening
ARM: 8933/1: replace Sun/Solaris style flag on section directive
ARM: 8932/1: Add clock_gettime64 entry point
ARM: 8931/1: Add clock_getres entry point
ARM: 8930/1: Add support for generic vDSO
ARM: 8929/1: use APSR_nzcv instead of r15 as mrc operand
ARM: 8927/1: ARM/hw_breakpoint: add more ARMv8 debug architecture versions support
ARM: 8918/2: only build return_address() if needed
ARM: 8928/1: ARM_ERRATA_775420: Spelling s/date/data/
ARM: 8925/1: tcm: include <asm/tcm.h> for missing declarations
ARM: 8924/1: tcm: make dtcm_end and itcm_end static
ARM: 8923/1: mm: include <asm/vga.h> for vga_base
ARM: 8922/1: parse_dt_topology() rate is pointer to __be32
ARM: 8920/1: share get_signal_page from signal.c to process.c
ARM: 8919/1: make unexported functions static
ARM: 8917/1: mm: include <asm/set_memory.h>
ARM: 8916/1: mm: make set_section_perms() static
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When the default processor handling was added to the function
cpu_v7_spectre_init() it only excluded other ARM implemented processor
cores. The Broadcom Brahma B53 core is not implemented by ARM so it
ended up falling through into the set of processors that attempt to use
the ARM_SMCCC_ARCH_WORKAROUND_1 service to harden the branch predictor.
Since this workaround is not necessary for the Brahma-B53 this commit
explicitly checks for it and prevents it from applying a branch
predictor hardening workaround.
Fixes: 10115105cb3a ("ARM: spectre-v2: add firmware based hardening")
Signed-off-by: Doug Berger <opendmb@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Rather than directly choosing which function to use based on
psci_ops.conduit, use the new arm_smccc_1_1 wrapper instead.
In some cases we still need to do some operations based on the
conduit, but the code duplication is removed.
No functional change.
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
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Now that we have arm_smccc_1_1_get_conduit(), we can hide the PSCI
implementation details from the arm spectre-v2 code, so let's do so.
As arm_smccc_1_1_get_conduit() implicitly checks that the SMCCC version
is at least SMCCC_VERSION_1_1, we no longer need to check this
explicitly where switch statements have a default case.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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In big.Little systems, some CPUs require the Spectre workarounds in
paths such as the context switch, but other CPUs do not. In order
to handle these differences, we need per-CPU vtables.
We are unable to use the kernel's per-CPU variables to support this
as per-CPU is not initialised at times when we need access to the
vtables, so we have to use an array indexed by logical CPU number.
We use an array-of-pointers to avoid having function pointers in
the kernel's read/write .data section.
Reviewed-by: Julien Thierry <julien.thierry@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Warn at error level if the context switching function is not what we
are expecting. This can happen with big.Little systems, which we
currently do not support.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Boot-tested-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
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Add firmware based hardening for cores that require more complex
handling in firmware.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Boot-tested-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
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In order to prevent aliasing attacks on the branch predictor,
invalidate the BTB or instruction cache on CPUs that are known to be
affected when taking an abort on a address that is outside of a user
task limit:
Cortex A8, A9, A12, A17, A73, A75: flush BTB.
Cortex A15, Brahma B15: invalidate icache.
If the IBE bit is not set, then there is little point to enabling the
workaround.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Boot-tested-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
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When the branch predictor hardening is enabled, firmware must have set
the IBE bit in the auxiliary control register. If this bit has not
been set, the Spectre workarounds will not be functional.
Add validation that this bit is set, and print a warning at alert level
if this is not the case.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Boot-tested-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
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