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2023-03-10ARM: zynq: Fix refcount leak in zynq_early_slcr_initQiheng Lin1-0/+1
[ Upstream commit 9eedb910a3be0005b88c696a8552c0d4c9937cd4 ] of_find_compatible_node() returns a node pointer with refcount incremented, we should use of_node_put() on error path. Add missing of_node_put() to avoid refcount leak. Fixes: 3329659df030 ("ARM: zynq: Simplify SLCR initialization") Signed-off-by: Qiheng Lin <linqiheng@huawei.com> Link: https://lore.kernel.org/r/20221129140544.41293-1-linqiheng@huawei.com Signed-off-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 151Thomas Gleixner1-10/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 675 mass ave cambridge ma 02139 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 35 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Armijn Hemel <armijn@tjaldur.nl> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.655028468@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-09-05ARM: zynq: Convert to using %pOFn instead of device_node.nameRob Herring1-1/+1
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Michal Simek <michal.simek@xilinx.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-09ARM: zynq: address L2 cache data corruptionJosh Cartwright1-0/+4
The Zynq has a bug where the L2 cache will return invalid data in some circumstances unless the L2C_RAM register is set to 0x00020202 before the first enabling of the L2 cache. The Xilinx-recommended solution to this problem is to ensure that early one of the earlier bootstages correctly initialize L2C_RAM, however, this issue wasn't discovered and fixed until after their EDK/SDK 14.4 release. For systems built prior to that, and which lack field-upgradable bootloaders, this issue still exists and silent data corruption can be seen in the wild. Fix these systems by ensuring L2C_RAM is properly initialized at the earliest convenient moment prior to the L2 being brought up, which is when the SLCR is first mapped. The Zynq bug is described in more detail by Xilinx AR# 54190 as quoted below. Xilinx AR# 54190 http://www.xilinx.com/support/answers/54190.htm Captured on 2014-09-24 14:43 -0500 = Description = For proper L2 cache operation, the user code must program the slcr.L2C_RAM register (address 0xF800_0A1C) to the value of 0x0002_0202 before enabling the L2 cache. The reset value (0x0001_0101) might cause, very infrequently, the L2 cache to return invalid data. = Solution = It is up to the user code (FSBL or other user code) to set the slcr.L2C_RAM register to the value 0x0002_0202 before enabling the L2 cache. Note: The L2 cache is disabled after reset and is not enabled by the BootROM. Note: The slcr.l2C_RAM register was previously reserved. It is added in the Zynq-7000 AP SoC Technical Reference Manual (TRM) v1.5 as "Reserved". Thanks to Jaeden Amero for initial debugging and triage efforts. Signed-off-by: Josh Cartwright <joshc@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-05-18ARM: zynq: Drop use of slcr_unlock in zynq_slcr_system_restartJosh Cartwright1-7/+0
The SLCR is unconditionally unlocked early on boot in zynq_slcr_init() and not ever re-locked. As such, it is not necessary to explicitly unlock in the restart codepath. Signed-off-by: Josh Cartwright <joshc@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-05-18ARM: zynq: Use restart_handler mechanism for slcr resetJosh Cartwright1-2/+19
By making use of the restart_handler chain mechanism, the SLCR-based reset mechanism can be prioritized amongst other mechanisms available on a particular board. Choose a default high-ish priority of 192 for this restart mechanism. Signed-off-by: Josh Cartwright <joshc@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-29ARM: zynq: Simplify SLCR initializationMichal Simek1-28/+7
Based on "mfd: syscon: Decouple syscon interface from platform devices" (sha1: bdb0066df96e74a4002125467ebe459feff1ebef) SLCR driver can use syscon/regmap drivers directly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-16ARM: zynq: Synchronise zynq_cpu_die/killSoren Brinkmann1-1/+42
Avoid races and add synchronisation between the arch specific kill and die routines. The same synchronisation issue was fixed on IMX platform by this commit: "ARM: imx: fix sync issue between imx_cpu_die and imx_cpu_kill" (sha1: 2f3edfd7e27ad4206acbc2ae99c9df5f46353024) Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20ARM: zynq: Add support for SOC_BUSMichal Simek1-0/+19
Provide information through SOC_BUS to user space. Silicon revision is provided through devcfg device. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-10ARM: zynq: Introduce zynq_slcr_unlock()Michal Simek1-2/+14
Call special function for unlocking SLCR. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-10ARM: zynq: Add and use zynq_slcr_read/write() helper functionsMichal Simek1-8/+48
Use zynq_slcr_read/write helper functions for reg access instead of readl/writel. Also use regmap when it is ready. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-10ARM: zynq: Make zynq_slcr_base staticSteffen Trumtrar1-1/+1
The pointer doesn't need to be passed around any more. Make it static. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-10ARM: zynq: Hang iomapped slcr address on device_nodeSteffen Trumtrar1-0/+2
For later usage by zynq clk driver. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-10ARM: zynq: Split slcr in two partsMichal Simek1-2/+24
Split the slcr into an early part for unlocking and cpu starting and a later syscon driver. Also add "syscon" compatible property for slcr. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-05ARM: zynq: Move clock_init from slcr to commonSteffen Trumtrar1-2/+0
Preparation step for next changes. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-07-26arm: zynq: slcr: Use read-modify-write for register writesSoren Brinkmann1-8/+8
zynq_slcr_cpu_start/stop() ignored the current register state when writing to a register. Fixing this by implementing proper read-modify-write. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-07-26arm: zynq: slcr: Clean up #definesSoren Brinkmann1-13/+12
Use a common naming scheme for register offset #defines: Some of those used a '_OFFSET' suffix to distinguish them from others. This scheme is used for all register offsets now. Separate the register offset #defines from others and sort them in increasing order. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-07-26arm: zynq: slcr: Remove redundant header #includesSoren Brinkmann1-10/+0
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-27arm: zynq: Migrate platform to clock controllerSoren Brinkmann1-1/+1
Migrate the Zynq platform and its drivers to use the new clock controller driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Cc: John Stultz <john.stultz@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.cz> Cc: linux-serial@vger.kernel.org Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-04-04arm: zynq: Add smp supportMichal Simek1-0/+29
Zynq is dual core Cortex A9 which starts always at zero. Using simple trampoline ensure long jump to secondary_startup code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
2013-04-04arm: zynq: Add support for system resetMichal Simek1-0/+27
Do system reset via slcr registers. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-04-04arm: zynq: Move slcr initialization to separate fileMichal Simek1-0/+69
Create separate slcr driver instead of polluting common code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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