starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2014-07-18	ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+	Russell King	1	-4/+4
2013-08-12	ARM: tegra: add LP1 suspend support for Tegra30	Joseph Lo	1	-4/+4
2013-07-19	ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15	Joseph Lo	1	-0/+22
2013-07-19	ARM: tegra: add a flag for tegra_disable_clean_inv_dcache to do LoUIS or ALL	Joseph Lo	1	-1/+6
2013-05-23	ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9	Joseph Lo	1	-3/+5
2013-01-28	ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode	Joseph Lo	1	-0/+19
2013-01-28	ARM: tegra: update the cache maintenance order for CPU shutdown	Joseph Lo	1	-1/+3
2012-11-16	ARM: tegra: retain L2 content over CPU suspend/resume	Joseph Lo	1	-0/+7
2012-11-16	ARM: tegra30: cpuidle: add powered-down state for CPU0	Joseph Lo	1	-0/+42
2012-11-16	ARM: tegra30: cpuidle: add powered-down state for secondary CPUs	Joseph Lo	1	-0/+29
2012-11-05	ARM: tegra: move iomap.h to mach-tegra	Stephen Warren	1	-1/+1
2012-09-13	ARM: tegra: clean up the common assembly macros into sleep.h	Joseph Lo	1	-32/+1
2012-06-11	ARM: tegra: Remove flow controller programming	Prashant Gaikwad	1	-29/+0
2012-03-26	ARM: tegra: Include assembler.h in sleep.S to fix build break	Stephen Warren	1	-1/+3
2012-02-06	ARM: tegra: assembler code for LP3	Peter De Schrijver	1	-0/+91