index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
arch
/
arm
/
mach-tegra
/
pm.h
Age
Commit message (
Expand
)
Author
Files
Lines
2014-07-17
ARM: tegra: Convert PMC to a driver
Thierry Reding
1
-9
/
+1
2014-05-30
ARM: l2c: tegra: convert to common l2c310 early resume functionality
Russell King
1
-2
/
+0
2013-09-17
ARM: tegra: delete stale header content
Stephen Warren
1
-3
/
+0
2013-08-12
ARM: tegra: add LP1 suspend support for Tegra20
Joseph Lo
1
-0
/
+2
2013-08-12
ARM: tegra: add LP1 suspend support for Tegra30
Joseph Lo
1
-0
/
+3
2013-08-12
ARM: tegra: add common LP1 suspend support
Joseph Lo
1
-0
/
+7
2013-06-05
ARM: tegra: don't pass CPU ID to tegra_{set,clear}_cpu_in_lp2
Joseph Lo
1
-2
/
+2
2013-04-18
ARM: tegra: pm: fix build error w/o PM_SLEEP
Joseph Lo
1
-1
/
+1
2013-04-04
ARM: tegra: cpuidle: remove redundant parameters for powered-down mode
Joseph Lo
1
-1
/
+1
2013-04-04
ARM: tegra: pm: add platform suspend support
Joseph Lo
1
-0
/
+15
2012-11-16
ARM: tegra: retain L2 content over CPU suspend/resume
Joseph Lo
1
-0
/
+2
2012-11-16
ARM: tegra30: cpuidle: add powered-down state for CPU0
Joseph Lo
1
-0
/
+3
2012-11-16
ARM: tegra30: cpuidle: add powered-down state for secondary CPUs
Joseph Lo
1
-0
/
+30