summaryrefslogtreecommitdiff
path: root/arch/arm/mach-tegra/iomap.h
AgeCommit message (Collapse)AuthorFilesLines
2015-07-16soc/tegra: fuse: Unify Tegra20 and Tegra30 driversThierry Reding1-3/+0
Unifying the drivers makes it easier to restrict the legacy probing paths to 32-bit ARM. This in turn will come in handy as support for new 64-bit ARM SoCs is added. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-15ARM: tegra: remove old LIC supportMarc Zyngier1-15/+0
Now that all DTs have been updated, entierely drop support for the non-DT code. This is likely to break platforms that do not update their DT, so print a warning at boot time. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088583-15097-7-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-12-04ARM: tegra: use section-sized static mappings for LPAE tooStephen Warren1-7/+7
The static mappings for Tegra's PPSB and APB regions were sized at 1MB in order to allow mapping via sections in order to avoid burning RAM for PTEs. On LPAE, sections are 2MB, so the static mappings need to be larger in order to gain the same benefit. Set IO_{PPSB,APB}_SIZE to SECTION_SIZE so this adjusts automatically. While we're fiddling with iomap.h, compress IO_{IRAM,CPU}_VIRT together to save virtual address space in the vmalloc region; these two regions are mapped using PTEs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-10-19ARM: tegra: add LP1 support code for Tegra124Joseph Lo1-0/+3
The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just need to update the difference of the register address, then we can continue to share the code. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-09-17ARM: tegra: remove much of iomap.hStephen Warren1-150/+0
iomap.h defines the base address of Tegra peripherals. Most of this information comes from device tree now, and hence can be deleted. Entries are kept for various system peripherals that low-level code (such as initial boot, system suspend/resume, debug) still requires. Removing the values removes the temptation for someone to use them. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-09-17ARM: tegra: move resume vector define to irammap.hStephen Warren1-2/+0
irammap.h's purpose is to define the layout/usage of IRAM. As such, TEGRA_IRAM_CODE_AREA should have been added there rather than iomap.h. Move the define, and rename it something more descriptive. Cc: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-13PCI: tegra: Move PCIe driver to drivers/pci/hostThierry Reding1-3/+0
Move the PCIe driver from arch/arm/mach-tegra into the drivers/pci/host directory. The motivation is to collect various host controller drivers in the same location in order to facilitate refactoring. The Tegra PCIe driver has been largely rewritten, both in order to turn it into a proper platform driver and to add MSI (based on code by Krishna Kishore <kthota@nvidia.com>) as well as device tree support. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> [swarren, split DT changes into a separate patch in another branch] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12ARM: tegra: add LP1 suspend support for Tegra114Joseph Lo1-0/+6
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The sequence when LP1 suspending: * tunning off L1 data cache and the MMU * storing some EMC registers, DPD (deep power down) status, clk source of mselect and SCLK burst policy * putting SDRAM into self-refresh * switching CPU to CLK_M (12MHz OSC) * tunning off PLLM, PLLP, PLLA, PLLC and PLLX * switching SCLK to CLK_S (32KHz OSC) * shutting off the CPU rail The sequence of LP1 resuming: * re-enabling PLLM, PLLP, PLLA, PLLC and PLLX * restoring the clk source of mselect and SCLK burst policy * setting up CCLK burst policy to PLLX * restoring DPD status and some EMC registers * resuming SDRAM to normal mode * jumping to the "tegra_resume" from PMC_SCRATCH41 Due to the SDRAM will be put into self-refresh mode, the low level procedures of LP1 suspending and resuming should be copied to TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before restoring the CPU context when resuming, the SDRAM needs to be switched back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy be restored. Then jumping to "tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore CPU context and back to kernel. Based on the work by: Bo Yan <byan@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12ARM: tegra: add common resume handling code for LP1 resumingJoseph Lo1-0/+2
Add support to the Tegra CPU reset vector to detect whether the CPU is resuming from LP1 suspend state. If it is, branch to the LP1-specific resume code. When Tegra enters the LP1 suspend state, the SDRAM controller is placed into a self-refresh state. For this reason, we must place the LP1 resume code into IRAM, so that it is accessible before SDRAM access has been re-enabled. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: remove USB address related macros from iomap.hVenu Byravarasu1-9/+0
USB register base address and sizes defined in iomap.h are not used in any files other than board-dt-tegra20.c. Hence removed those defines from header file and using the absolute values in board files. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16ARM: tegra: simplify DEBUG_LL UART selection optionsStephen Warren1-14/+0
Delete CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH; it's not useful any more: * No upstream bootloader currently or will ever support this option. * CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA is a much more direct alternative. Merge the fixed and automatic UART selection menus into a single choice for simplicity; now you either pick AUTO_ODMDATA or a single fixed UART, rather than potentially having an AUTO option override whatever fixed option was chosen. Remove TEGRA_DEBUG_UART_NONE; if you don't want a Tegra DEBUG_LL UART, simply don't turn on DEBUG_LL. NONE used to be the default option, so pick AUTO_ODMDATA as the new default. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-05ARM: tegra: move iomap.h to mach-tegraStephen Warren1-0/+323
Nothing outside mach-tegra uses this file, so there's no need for it to be in <mach/>. Since uncompress.h and debug-macro.S remain in include/mach, they need to include "../../iomap.h" becaue of this change. uncompress.h will soon be deleted in later multi-platform/single-zImage patches. debug-macro.S will need to continue to include this header using an explicit relative path, to avoid duplicating the physical->virtual address mapping that iomap.h dictates. Signed-off-by: Stephen Warren <swarren@nvidia.com>