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With the CMA changes from Joonsoo Kim <iamjoonsoo.kim@lge.com>, it
was noticed that n900 stopped booting. After investigating it turned
out that n900 save_secure_ram_context does some whacky virtual to
physical address translation for the SRAM data address.
As we now only have minimal parts of omap3 idle code copied to SRAM,
running save_secure_ram_context() in SRAM is not needed. It only gets
called on PM init. And it seems there's no need to ever call this from
SRAM idle code.
So let's just keep save_secure_ram_context() in DDR, and pass it the
physical address of the parameters. We can do everything else in
omap-secure.c like we already do for other secure code.
And since we don't have any documentation, I still have no clue what
the values for 0, 1 and 1 for the parameters might be. If somebody has
figured it out, please do send a patch to add some comments.
Debugged-by: Joonsoo Kim <iamjoonsoo.kim@lge.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Shared interrupts with IRQ_NOAUTOEN got a warning added with commit
04c848d39879 ("genirq: Warn when IRQ_NOAUTOEN is used with shared
interrupts").
Let's just drop the IRQ_NOAUTOEN use for omap3 PRM shared interrupt as
it does not seem to cause any other issues based on my testing. We have
moved a lot of the code to initialize later, and whatever problems the
legacy booting had seem to be gone now with pinctrl driver and device
tree based booting.
Otherwise we will get:
WARNING: CPU: 0 PID: 1 at kernel/irq/manage.c:1348 __setup_irq+0x5d0/0x64c
[<c01b0260>] (__setup_irq) from [<c01b0480>]
(request_threaded_irq+0xdc/0x188)
[<c01b0480>] (request_threaded_irq) from [<c051c780>]
(pcs_probe+0x6ec/0x8a4)
[<c051c780>] (pcs_probe) from [<c05a84b8>] (platform_drv_probe+0x50/0xb0)
[<c05a84b8>] (platform_drv_probe) from [<c05a6288>]
(driver_probe_device+0x33c/0x478)
Note that we also need to remove the related enable_irq() to avoid
getting the following:
WARNING: CPU: 0 PID: 1 at kernel/irq/manage.c:529 enable_irq+0x34/0x70
[<c01afa04>] (enable_irq) from [<c0c0f1fc>] (omap3_pm_init+0x118/0x3f8)
[<c0c0f1fc>] (omap3_pm_init) from [<c0c0ae7c>] (am35xx_init_late+0x10/0x18)
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Depending on timing during the resume path from off mode on 36xx, we may
see external aborts. These seem to be caused by the following:
- OMAP3 Advisory 1.62 "MPU Cannot Exit from Standby" says we need to
disable intc autoidle before WFI
- DM3730 Advisory 1.106 "MPU Leaves MSTANDBY State Before IDLEREQ of
Interrupt Controller is Released" says we need to wait before
accessing intc
omap3_intc_resume_idle restores the intc autoidle for all resume paths,
however in the resume path from off mode only it is also being restored
by omap_intc_restore_context before this call to omap3_intc_resume_idle
happens. The second restore of the intc autoidle in this path is what
appears to be causing the external abort so for the off mode resume path
let's rely on omap_intc_restore_context to restore intc autoidle, and
for all other paths let omap3_intc_resume_idle handle it as it is now.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The cpuidle tracepoints are called within a rcu_idle_exit() section, and
must be denoted with the _rcuidle() version of the tracepoint.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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OMAP2/3 now use generic API for the prm_clear_mod_irqs, the SoC specific
implementation details are provided through prm_ll_data.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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This makes the API the same as used with OMAP2, and makes it possible
to implement a generic driver API for the functionality.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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We still need to support platform data for omap3 until it's booting
in device tree only mode. So let's add platform_data/omap-gpmc.h for
that, and a minimal linux/omap-gpmc.h for the save and restore used
by the PM code.
Let's also keep a minimal mach-omap2/gpmc.h still around to avoid
churn on the board-*.c files. Once omap3 boots in device tree only
mode, we can drop mach-omap2/gpmc.h and we can make the data
structures in platform_data/omap-gpmc.h private to the GPMC driver.
Note that we can now also remove gpmc-nand.h and gpmc-onenand.h.
Cc: Arnd Bergmann <arnd@arndb.de>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Use the more common pr_warn.
Other miscellanea:
o Realign arguments
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Control module related PM initializations are now moved within control
module driver. Done in preparation to isolate the code to its own driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Done in preparation to move PRM into its own driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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This patch moves the functionality from PM core to control driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Helps to isolate the PRM driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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This is a more proper isolation of the code. Done in preparation of making
PRM an individual driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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This is a more proper isolation of the code. Done in preparation of making
PRM an individual driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Done in preparation to make the prm an individual driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Merge "ARM: omap pm changes for v3.16 merge window, resend" from Tony Lindgren:
PM related fixes for omap3 that were discovered during omap3
conversion to device tree. This series sets up the PMIC signaling
in a way where we can test for PM regressions easily by
looking at state of the the sys_clkreq and sys_off_mode pins.
Note that this series alone does not make omap3 PM to cut
off core voltage during off-idle, changes to twl4030-power.c
configurations are still needed. Those will be posted
separately.
* tag 'omap-for-v3.16/pm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Enable CPUidle in omap2plus_defconfig
ARM: dts: Enable N900 keyboard sleep leds by default
ARM: OMAP2+: Fix voltage scaling init for device tree
ARM: dts: Configure omap3 twl4030 I2C4 pins by default
ARM: OMAP3: Fix voltage control for deeper idle states
ARM: OMAP3: Disable broken omap3_set_off_timings function
ARM: OMAP3: Fix idle mode signaling for sys_clkreq and sys_off_mode
ARM: dts: Fix omap serial wake-up when booted with device tree
mfd: twl-core: Fix idle mode signaling for omaps when booted with device tree
Signed-off-by: Olof Johansson <olof@lixom.net>
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In omap2_common_pm_late_init suspend_set_ops was called to set common
suspend handling functions for all omap platforms. This created two
problems. First, these suspend ops were being set for all platforms,
regardless of whether or not suspend support has been integrated so in
the case of AM33XX, suspend to mem was presented as available but
failed every time. Second, some platforms will need to define a
completely separate set of suspend ops, such as AM33XX, due to
differences from previous omap platforms so there is no need to
always set the common omap ops.
This patch moves the suspend_set_ops call from omap2_common_pm_late_init
into a separate function that then gets called in the omap*_pm_init
functions for each platform.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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While debugging legacy mode vs device tree booted PM regressions,
I noticed that omap3 is not toggling sys_clkreq and sys_off_mode
pins like it should.
The sys_clkreq and sys_off_mode pins are not toggling because of
the following issues:
1. The default polarity for the sys_off_mode pin is wrong.
OFFMODE_POL needs to be cleared for sys_off_mode to go down when
hitting off-idle, while CLKREQ_POL needs to be set so sys_clkreq
goes down when hitting retention.
2. The values for voltctrl register need to be updated dynamically.
We need to set either the retention idle bits, or off idle bits
in the voltctrl register depending the idle mode we're targeting
to hit.
Let's fix these two issues as otherwise the system will just
hang if any twl4030 PMIC idle scripts are loaded. The only case
where the system does not hang is if only retention idle over I2C4
is configured by the bootloader.
Note that even without the twl4030 PMIC scripts, these fixes will
do the proper signaling of sys_clkreq and sys_off_mode pins, so
the fixes are needed to fix monitoring of PM states with LEDs or
an oscilloscope.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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There is a solitary write to this register every wakeup from off-mode,
which isn't doing anything, so remove it.
Also note that modifying this register trashes any attempted
voltage scaling configuration and the change probably should
never have gotten merged in the first place.
Cc: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[tony@atomide.com: updated comments to describe regression]
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Some omap3 code is throwing a warning:
arch/arm/mach-omap2/pm34xx.c: In function 'omap3_save_secure_ram_context':
arch/arm/mach-omap2/pm34xx.c:123:32: warning: cast to pointer from
integer of different size [-Wint-to-pointer-cast]
In reality this code will never actually execute with LPAE=y, since
Cortex-A8 doesn't support it. So downcasting the __pa() is safe in
this case.
Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Tony Lindgren <tony@atomide.com>
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OMAP3 PM core requires IVA2 bootmode to be set to idle during init. Currently,
a direct register write is used for this. Add a new ctrl API for this purpose
instead.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists)
changed PM to not access IVA registers on omaps that don't have
them. Turns out we still need to idle iva2 as otherwise
iva2_pwrdm will stay on and block deeper idle states.
It seems that the only part of the reset that may not be needed
is the setting of the iva2 boot mode to idle. But as that register
seems to be there and is harmless if no iva2 is on the SoC, it's
probably safest to do the complete reset.
Acked-by: Mark A. Greer <mgreer@animalcreek.com>
Acked-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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On OMAP platform, FIQ is reserved for secure environment only. If at all
the FIQ needs to be disabled, it involves going through security
API call. Hence the local_fiq_[enable/disable]() in the OMAP code is bogus.
On GP devices too, the fiq is disabled for non-secure software.
So just get rid of it.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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The text in Documentation said it would be removed in 2.6.41;
the text in the Kconfig said removal in the 3.1 release. Either
way you look at it, we are well past both, so push it off a cliff.
Note that the POWER_CSTATE and the POWER_PSTATE are part of the
legacy tracing API. Remove all tracepoints which use these flags.
As can be seen from context, most already have a trace entry via
trace_cpu_idle anyways.
Also, the cpufreq/cpufreq.c PSTATE one is actually unpaired, as
compared to the CSTATE ones which all have a clear start/stop.
As part of this, the trace_power_frequency also becomes orphaned,
so it too is deleted.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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Based on earlier discussions[1] we attempted to find a suitable
location for the omap DMA header in commit 2b6c4e73 (ARM: OMAP:
DMA: Move plat/dma.h to plat-omap/dma-omap.h) until the conversion
to dmaengine is complete.
Unfortunately that was before I was able to try to test compile
of the ARM multiplatform builds for omap2+, and the end result
was not very good.
So I'm creating yet another all over the place patch to cut the
last dependency for building omap2+ for ARM multiplatform. After
this, we have finally removed the driver dependencies to the
arch/arm code, except for few drivers that are being worked on.
The other option was to make the <plat-omap/dma-omap.h> path
to work, but we'd have to add some new header directory to for
multiplatform builds.
Or we would have to manually include arch/arm/plat-omap/include
again from arch/arm/Makefile for omap2+.
Neither of these alternatives sound appealing as they will
likely lead addition of various other headers exposed to the
drivers, which we want to avoid for the multiplatform kernels.
Since we already have a minimal include/linux/omap-dma.h,
let's just use that instead and add a note to it to not
use the custom omap DMA functions any longer where possible.
Note that converting omap DMA to dmaengine depends on
dmaengine supporting automatically incrementing the FIFO
address at the device end, and converting all the remaining
legacy drivers. So it's going to be few more merge windows.
[1] https://patchwork.kernel.org/patch/1519591/#
cc: Russell King <linux@arm.linux.org.uk>
cc: Kevin Hilman <khilman@ti.com>
cc: "Benoît Cousson" <b-cousson@ti.com>
cc: Herbert Xu <herbert@gondor.apana.org.au>
cc: "David S. Miller" <davem@davemloft.net>
cc: Vinod Koul <vinod.koul@intel.com>
cc: Dan Williams <djbw@fb.com>
cc: Mauro Carvalho Chehab <mchehab@infradead.org>
cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
cc: David Woodhouse <dwmw2@infradead.org>
cc: Kyungmin Park <kyungmin.park@samsung.com>
cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
cc: Hans Verkuil <hans.verkuil@cisco.com>
cc: Vaibhav Hiremath <hvaibhav@ti.com>
cc: Lokesh Vutla <lokeshvutla@ti.com>
cc: Rusty Russell <rusty@rustcorp.com.au>
cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
cc: Afzal Mohammed <afzal@ti.com>
cc: linux-crypto@vger.kernel.org
cc: linux-media@vger.kernel.org
cc: linux-mtd@lists.infradead.org
cc: linux-usb@vger.kernel.org
cc: linux-fbdev@vger.kernel.org
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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omap-for-v3.8/cleanup-headers-prepare-multiplatform-v3
omap prcm changes via Paul Walmsley <paul@pwsan.com>:
Some miscellaneous OMAP hwmod changes for 3.8, along with a PRM
change needed for one of the hwmod patches to function.
Basic test logs for this branch on top of Tony's
omap-for-v3.8/clock branch at commit
558a0780b0a04862a678f7823215424b4e5501f9 are here:
http://www.pwsan.com/omap/testlogs/hwmod_devel_a_3.8/20121121161522/
However, omap-for-v3.8/clock at 558a0780 does not include some fixes
that are needed for a successful test. With several reverts,
fixes, and workarounds applied, the following test logs were
obtained:
http://www.pwsan.com/omap/testlogs/TEST_hwmod_devel_a_3.8/20121121162719/
which indicate that the series tests cleanly.
Conflicts:
arch/arm/mach-omap2/cm33xx.c
arch/arm/mach-omap2/io.c
arch/arm/mach-omap2/prm_common.c
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arch/arm/mach-omap2/prcm.c and arch/arm/plat-omap/include/plat/prcm.h
are now completely unused and can be removed.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
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Most of the defines are specific to omap1 and omap2+,
and should be in the local headers. Only minimal function
prototypes need to be shared.
As discussed on linux-arm-kernel, we want to avoid
relative includes for the arch/arm/*omap* shared code:
http://www.spinics.net/lists/linux-omap/msg80520.html
So this patch re-adds a minimal plat/sram.h.
The new plat/sram.h must not be included from drivers,
that will break build for omap2+ CONFIG_MULTIPLATFORM.
Note that this patch temporarily adds two more
relative includes; Those will be removed in the
following patch.
Signed-off-by: Tony Lindgren <tony@atomide.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.8/cleanup-prcm
The first set of OMAP PRM/CM-related cleanup patches for 3.8.
Prepares for the future move of the PRM/CM code to drivers/. Also
includes some prcm.[ch] cleanup patches from the WDTIMER cleanup
series that don't need external acks.
Basic test logs for this branch on top of v3.7-rc2 are here:
http://www.pwsan.com/omap/testlogs/prcm_cleanup_a_3.8/20121021123719/
But due to the number of unrelated regressions present in v3.7-rc[12],
it's not particularly usable as a testing base. With reverts, fixes,
and workarounds applied as documented in:
http://www.pwsan.com/omap/testlogs/test_v3.7-rc2/20121020134755/README.txt
the following test logs were obtained:
http://www.pwsan.com/omap/testlogs/prcm_cleanup_a_3.8/20121020231757/
which indicate that the series tests cleanly.
Conflicts:
arch/arm/mach-omap2/Makefile
arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
arch/arm/mach-omap2/pm24xx.c
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On OMAP34xx/35xx, and OMAP36xx chips with ES < 1.2, if the PER
powerdomain goes to OSWR or OFF while CORE stays at CSWR or ON, or if,
upon chip wakeup from OSWR or OFF, the CORE powerdomain goes ON before
PER, the UART3/4 FIFOs and McBSP2/3 SIDETONE memories will be
unusable. This is erratum i582 in the OMAP36xx Silicon Errata
document.
This patch implements one of several parts of the workaround: the
addition of the wakeup dependency between the PER and WKUP
clockdomains, such that PER will wake up at the same time CORE_L3
does.
This is not a complete workaround. For it to be complete:
1. the PER powerdomain's next power state must not be set to OSWR or
OFF if the CORE powerdomain's next power state is set to CSWR or
ON;
2. the UART3/4 FIFO and McBSP2/3 SIDETONE loopback tests should be run
if the LASTPOWERSTATEENTERED bits for PER and CORE indicate that
PER went OFF while CORE stayed on. If loopback tests fail, then
those devices will be unusable until PER and CORE can undergo a
transition from ON to OSWR/OFF and back ON.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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Move OMAP3xxx-specific CM functions & macros into cm3xxx.[ch] and
OMAP2xxx-specific macros into cm2xxx.[ch]. Move basic CM register
access functions into static inline functions in cm2xxx_3xxx.h,
leaving only OMAP2/3 hardreset functions in cm2xxx_3xxx.c.
As part of this, split the CM and hwmod code that waits for devices to
become ready into SoC-specific functions.
This is in preparation for the upcoming move of this code to drivers/.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Reviewed-by: Russ Dill <Russ.Dill@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Move OMAP3xxx-specific PRM functions & macros into prm3xxx.[ch] and
OMAP2xxx-specific macros into prm2xxx.h. (prm2xxx.c will be created
by a subsequent patch when it's needed.) Move basic PRM register
access functions into static inline functions in prm2xxx_3xxx.h, leaving
only OMAP2/3 hardreset functions in prm2xxx_3xxx.c.
Also clarify the initcall function naming to reinforce that this code
is specifically for the PRM IP block.
This is in preparation for the upcoming powerdomain series and the
upcoming move of this code to drivers/.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Reviewed-by: Russ Dill <Russ.Dill@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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We want to remove plat/cpu.h. To do this, let's first split
it to private soc.h to mach-omap1 and mach-omap2. We have to
keep plat/cpu.h around until the remaining drivers are fixed,
so let's include the local soc.h in plat/cpu.h and for drivers
still including plat/cpu.h.
Once the drivers are fixed not to include plat/cpu.h, we
can remove the file.
This is needed for the ARM common zImage support.
[tony@atomide.com: updated to not print a warning]
Signed-off-by: Tony Lindgren <tony@atomide.com>
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We can move this from plat to be local to plat-omap
for common ARM zImage support.
Signed-off-by: Tony Lindgren <tony@atomide.com>
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omap-for-v3.8/cleanup-headers
Conflicts:
arch/arm/mach-omap2/board-omap3logic.c
arch/arm/mach-omap2/gpmc.c
drivers/media/platform/omap/omap_vout.c
drivers/media/platform/omap/omap_vout_vrfb.c
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omap-for-v3.8/cleanup-headers
Conflicts:
arch/arm/mach-omap2/board-3430sdp.c
arch/arm/mach-omap2/board-h4.c
arch/arm/mach-omap2/board-rx51-peripherals.c
arch/arm/mach-omap2/board-rx51.c
arch/arm/mach-omap2/pm34xx.c
drivers/mtd/nand/omap2.c
drivers/mtd/onenand/omap2.c
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Remove arch/arm/plat-omap/include/plat/sdrc.h by folding its contents
into arch/arm/mach-omap2/sdrc.h. The objective is to assist Tony in
cleaning out arch/arm/plat-omap/, as his upstreams request.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
[tony@atomide.com: updated to remove rotate macros]
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Move plat/dma.h to plat-omap/dma-omap.h as part of single
zImage work
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Requirement of gpmc header outside of mach-omap2 has been
cutoff, move gpmc header file in plat-omap folder to local
mach-omap2 folder
Objective - common zImage participation of omap
Signed-off-by: Afzal Mohammed <afzal@ti.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into cleanup-makefile-sparse
smatch and string-wrapping cleanups for the OMAP subarch code.
These changes fix some of the more meaningful warnings that smatch
returns for the OMAP subarch code, and unwraps strings that are
wrapped at the 80-column boundary, to conform with the current
practice.
Basic build, boot, and PM logs are available here:
http://www.pwsan.com/omap/testlogs/warnings_a_cleanup_3.7/20120912025927/
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This way we can remove includes of plat/gpio.h which won't work
with the single zImage support.
Note that we also remove the cpu_class_is_omap2() check
in gpio-omap.c as the drivers should not call it as we need to
make it local to arch/arm/mach-omap2 for single zImage support.
While at it, arrange the related includes in the standard way.
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: linux-mtd@lists.infradead.org
Cc: alsa-devel@alsa-project.org
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Find and unwrap wrapped strings in the style:
pr_debug("clockdomain: hardware cannot set/clear wake up of "
"%s when %s wakes up\n", clkdm1->name, clkdm2->name);
Keeping these strings contiguous seems to be the current Linux kernel
policy.
The offending lines were found with the following command:
pcregrep -rnM '"\s*$\s*"' arch/arm/*omap*
While here, some messages have been clarified, some pr_warning(
... calls have been converted to pr_warn( ..., and some printk(KERN_*
... have been converted to pr_*.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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This reverts commit 58f0829b7186150318c79515f0e0850c5e7a9c89.
Converstion to per-pwrdm per/post transition calls was a bit
premature. Only tracking MPU, PER & CORE in the idle path means we
lose the accounting for all the other powerdomains which may also
transition in idle. On OMAP3, due to autodeps, several powerdomains
transition along with MPU (e.g. DSS, USBHOST), and the accounting for
these was lost with this patch. Since the accounting includes the
context loss counters, drivers for devices in those power domains
would never notice context lost, so would likely hang after any
off-mode transitions.
This patch should be revisited when the upcoming clkdm/pwrmdm/voltdm
use-counting seires is merged since then we can properly do accounting
without relying on a call in the idle path.
In addition, the original patch had another bug because the PER
powerdomain accounting was not updated until after the GPIO resume
hook is called. Since gpio_resume_after_idle() checks the context
loss count (which is not yet updated) it would not properly restore
context, leaving the GPIO banks in an undefined state.
Cc: Jean Pihet <jean.pihet@newoldbits.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Reported-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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Pull arm-soc power management changes from Arnd Bergmann:
"These are various power management related changes, mainly concerning
cpuidle on i.MX and OMAP, as well as a the move of the omap
smartreflex driver to live in the power subsystem."
Fix up conflicts in arch/arm/mach-{imx/mach-imx6q.c,omap2/prm2xxx_3xxx.h}
* tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits)
ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-merge
ARM: OMAP2+: do not allow SmartReflex to be built as a module
ARM: OMAP2: Use hwmod to initialize mmc for 2420
ARM: OMAP3: PM: cpuidle: optimize the clkdm idle latency in C1 state
ARM: OMAP3: PM: cpuidle: optimize the PER latency in C1 state
ARM: OMAP3: PM: cpuidle: default to C1 in next_valid_state
ARM: OMAP3: PM: cleanup cam_pwrdm leftovers
ARM: OMAP3: PM: call pre/post transition per powerdomain
ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdm
ARM: OMAP3: PM: Remove IO Daisychain control from cpuidle
ARM: OMAP3PLUS: hwmod: reconfigure IO Daisychain during hwmod mux
ARM: OMAP3+: PRM: Enable IO wake up
ARM: OMAP4: PRM: Add IO Daisychain support
ARM: OMAP3: PM: Move IO Daisychain function to omap3 prm file
ARM: OMAP3: PM: correct enable/disable of daisy io chain
ARM: OMAP2+: PRM: fix compile for OMAP4-only build
W1: OMAP HDQ1W: use runtime PM
ARM: OMAP2+: HDQ1W: use omap_device
W1: OMAP HDQ1W: use 32-bit register accesses
W1: OMAP HDQ1W: allow driver to be built on all OMAP2+
...
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git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into fixes-non-critical
Some OMAP AM35xx fixes.
The powerdomain and clockdomain data for the AM35xx are finally fixed.
The AM35xx EMAC/MDIO Ethernet controller integration code has been
converted to use the OMAP device and hwmod framework. Also the UART4
and HSOTGUSB warnings have been fixed.
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commit e7410cf7 (OMAP3: PM: move device-specific special cases from PM
core into CPUidle) moved mangement of cam_pwrdm to CPUidle but left
some remnants behind, namely the call to clkcm_allo_idle() for the
clockdomains in the MPU pwrdm. Remove these since they are not
necessary and cause unwanted latency in the idle path.
Acked-by: Tero Kristo <Tero Kristo <t-kristo@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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We only need to call the pre/post transtion methods when we know the
power state is changing. First, split up the pre/post transition
calls to be per-powerdomain, and then make them conditional on whether
the power domain is actually changing states.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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Iteration over all power domains in the idle path is unnecessary since
only power domains that are transitioning need to be accounted for.
Also PRCM register accesses are known to be expensive, so the
additional latency added to the idle path is signficiant.
In order allow the pre/post transitions to be isolated and called
per-pwrdm, change the API so passing in a specific power domain will
trigger the pre/post transtion accounting for only that specific power
domain. Passing NULL means iterating over all power domains as is
current behavior.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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